DS3184中文资料
GENERAL DESCRIPTION
The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate ATM cell/HDLC packet processor(s) with a DS3/E3 framer(s) and LIU(s) to map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed, E3-framed, or clear-channel data streams on per-port basis.
APPLICATIONS
Access Concentrators SONET/SDH ADM Multiservice Access Platform (MSAP) SONET/SDH Muxes PBXs
Multiservice Protocol Platform (MSPP) Digital Cross Connect Test Equipment
ATM and Frame Relay Equipment Routers and Switches Integrated Access Device (IAD)
PDH Multiplexer/ Demultiplexer
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS3181* 0°C to +70°C 400 TE-CSBGA (27mm x
27mm, 1.27mm pitch) DS3181N* -40°C to +85°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3182* 0°C to +70°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3182N* -40°C to +85°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3183* 0°C to +70°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3183N* -40°C to +85°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3184 0°C to +70°C 400 TE-CSBGA (27mm x 27mm, 1.27mm pitch) DS3184N
-40°C to +85°C
400 TE-CSBGA (27mm x 27mm, 1.27mm pitch)
*Future product—contact factory for availability.
FEATURES
§ Single (DS3181), Dual (DS3182), Triple
(DS3183), or Quad (DS3184) with Integrated LIU ATM/Packet PHYs for DS3, E3, and Clear-Channel 52Mbps (CC52)
§ Pin Compatible for Ease of Port Density
Migration in the Same PC Board Platform
§ Each Port Independently Configurable
§ Perform Receive Clock/Data Recovery and
Transmit Waveshaping
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3) or 440 Meters or 1443 Feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx § Universal PHYs Map ATM Cells and/or HDLC
Packets into DS3 or E3 Data Streams
§ UTOPIA L2/L3 or POS-PHY? L2/L3 or SPI-3
Interface with 8-, 16-, or 32-Bit Bus Width
§ 66MHz UTOPIA L3 and POS-PHY L3 Clock § 52MHz UTOPIA L2 and POS-PHY L2 Clock § Ports Independently Configurable for Cell or
Packet Traffic in POS-PHY Bus Modes § Direct, PLCP, DSS, and Clear-Channel Cell
Mapping
DS3181/DS3182/DS3183/DS3184
Single/Dual/Triple/Quad
ATM/Packet PHYs with Built-In LIU
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
DS3181/DS3182/DS3183/DS3184 FEATURES (continued)
§ Direct and Clear-Channel Packet Mapping
§ On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s)
§ Ports Independently Configurable for DS3, E3 (Full or Subrate) or Arbitrary Framing Protocols
Up to 52Mbps
§ Programmable (Externally Controlled or
Internally Finite State Machine Controlled)
Subrate DS3/E3
§ Full-Featured DS3/E3/PLCP Alarm Generation and Detection
§ Built-In HDLC Controllers with 256-Byte FIFOs for Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes and PLCP NR/GC
Bytes
§ On-Chip BERTs for PRBS and Repetitive Pattern Generation, Detection, and Analysis
§ Large Performance-Monitoring Counters for Accumulation Intervals of at Least 1 Second
§ Flexible Overhead Insertion/Extraction Ports for DS3, E3, and PLCP Framers § Loopbacks Include Line, Diagnostic, Framer, Payload, Analog, and System Interface with
Capabilities to Insert AIS in the Directions Away
from Loopback Directions
§ Ports can be Disabled to Reduce Power
§ Integrated Clock Rate Adapter to Generate the Remaining Internally Required 44.736MHz
(DS3), 34.368MHz (E3), and 52MHz (Arbitrary
Framing at Up to 52Mbps) from a Single Clock
Reference Source at One of Those Three
Frequencies
§ Pin Compatible with the DS3171/2/3/4 Family and the DS3161/2/3/4 Family
§ 8/16-Bit Generic Microprocessor Interface
§ Low-Power (2.7W typ) 3.3V Operation (5V-Tolerant I/O)
§ Small, High-Density, Thermally Enhanced, Chip-Scale BGA Packaging (TE-CSBGA) with 1.27mm Pin Pitch
§ Industrial Temperature Operation:
-40°C to +85°C
§ IEEE1149.1 JTAG Test Port
DETAILED DESCRIPTION
The DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs perform all the functions necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3 (34.368Mbps) framed, or 52Mbps clear-channel data streams on DS3, E3, or STS-1 physical copper lines. Each line interface unit (LIU) has independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal or can be bypassed for direct clock and data inputs. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU drives standard pulse-shape waveforms onto 75W coaxial cable or can be bypassed for direct clock and data outputs. The jitter attenuator can be placed in either transmit or receive data path when the LIU is enabled. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3, or G.832 E3 data streams. PLCP framers provide legacy ATM transmission-convergence support. DSS scrambling is performed for clear-channel ATM cell support. With integrated hardware support for both cells and packets, the DS318x DS3/E3 ATM/Packet PHYs provide system on-chip solutions (from DS3/E3/STS-1 physical copper lines to ATM/Packet UTOPIA/POS-PHY Level 2/3 system switch) for universal high-density line cards in the unchannelized DS3/E3/clear-channel DS3 ATM/Packet applications. Unused functions can be powered down to reduce device power. The DS318x ATM/Packet PHYs with embedded LIU conform to the telecommunications standards listed in Section 4.
DS3181/DS3182/DS3183/DS3184
TABLE OF CONTENTS
1BLOCK DIAGRAMS 14 2APPLICATIONS 15 3FEATURE DETAILS 17
3.1G LOBAL F EATURES (17)
3.2R ECEIVE DS3/E3/STS-1 LIU F EATURES (17)
3.3R ECEIVE DS3/E3 F RAMER F EATURES (17)
3.4R ECEIVE PLCP F RAMER F EATURES (18)
3.5R ECEIVE C ELL P ROCESSOR F EATURES (18)
3.6R ECEIVE P ACKET P ROCESSOR F EATURES (18)
3.7R ECEIVE FIFO F EATURES (19)
3.8R ECEIVE S YSTEM I NTERFACE F EATURES (19)
3.9T RANSMIT S YSTEM I NTERFACE F EATURES (19)
3.10T RANSMIT FIFO F EATURES (19)
3.11T RANSMIT C ELL P ROCESSOR F EATURES (19)
3.12T RANSMIT P ACKET P ROCESSOR F EATURES (19)
3.13T RANSMIT PLCP F ORMATTER F EATURES (20)
3.14T RANSMIT DS3/E3 F ORMATTER F EATURES (20)
3.15T RANSMIT DS3/E3/STS-1 LIU F EATURES (20)
3.16J ITTER A TTENUATOR F EATURES (20)
3.17C LOCK R ATE A DAPTER F EATURES (20)
3.18HDLC O VERHEAD C ONTROLLER F EATURES (20)
3.19FEAC C ONTROLLER F EATURES (21)
3.20T RAIL T RACE B UFFER F EATURES (21)
3.21B IT E RROR R ATE T ESTER (BERT) F EATURES (21)
3.22L OOPBACK F EATURES (21)
3.23M ICROPROCESSOR I NTERFACE F EATURES (21)
3.24S UBRATE F EATURES (F RACTIONAL DS3/E3) (21)
3.25T EST F EATURES (22)
4STANDARDS COMPLIANCE 23 5ACRONYMS AND GLOSSARY 25 6MAJOR OPERATIONAL MODES 26
6.1DS3/E3 ATM/P ACKET M ODE (26)
6.2DS3/E3 ATM/P ACKET—OHM M ODE (27)
6.3DS3/E3 I NTERNAL F RACTIONAL (S UBRATE) ATM/P ACKET M ODE (28)
6.4DS3/E3 E XTERNAL F RACTIONAL (S UBRATE) ATM/P ACKET M ODE (29)
6.5DS3/E3 F LEXIBLE E XTERNAL F RACTIONAL (S UBRATE) M ODE C ONFIGURATION M ODE (30)
6.6DS3/E3 G.751 PLCP ATM M ODE (31)
6.7DS3/E3 G.751 PLCP ATM—OHM M ODE (32)
6.8C LEAR-C HANNEL ATM/P ACKET M ODE (34)
6.9C LEAR-C HANNEL ATM/P ACKET—OHM M ODE (35)
6.10C LEAR-C HANNEL O CTET A LIGNED ATM/P ACKET—OHM M ODE (36)
7MAJOR LINE INTERFACE OPERATING MODES 37
7.1DS3HDB3/B3ZS/AMI LIU M ODE (37)
7.2HDB3/B3ZS/AMI N ON-LIU L INE I NTERFACE M ODE (39)
7.3UNI L INE I NTERFACE M ODE (40)
7.4UNI L INE I NTERFACE—OHM M ODE (41)
8PIN DESCRIPTIONS 42
8.1S HORT P IN D ESCRIPTIONS (42)
8.2D ETAILED P IN D ESCRIPTIONS (47)
8.3P IN F UNCTIONAL T IMING (66)
8.3.1Line IO (66)
DS3181/DS3182/DS3183/DS3184
8.3.3Internal (IFRAC) and External (XFRAC) Fractional DS3/E3 Overhead Functional Timing (72)
8.3.4Flexible Fractional (FFRAC) DS3/E3 Overhead Interface Functinal Timing (73)
8.3.5UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing (75)
8.3.6Microprocessor Interface Functional Timing (88)
8.3.7JTAG Functional Timing (92)
9INITIALIZATION AND CONFIGURATION 93
9.1M ONITORING AND D EBUGGING (95)
9.1.1Cell/Packet FIFO (95)
9.1.2Cell Processor (95)
9.1.3Packet Processor (96)
10FUNCTIONAL DESCRIPTION 97
10.1P ROCESSOR B US I NTERFACE (97)
10.1.18/16-Bit Bus Widths (97)
10.1.2Ready Signal (RDY) (97)
10.1.3Byte Swap Modes (97)
10.1.4Read-Write / Data Strobe Modes (97)
10.1.5Clear on Read / Clear on Write Modes (97)
10.1.6Global Write Method (98)
10.1.7Interrupt and Pin Modes (98)
10.1.8Interrupt Structure (98)
10.2C LOCKS (99)
10.2.1Line Clock Modes (99)
10.2.2Sources of Clock Output Pin Signals (101)
10.2.3Line IO Pin Timing Source Selection (103)
10.2.4Clock Structures On Signal IO Pins (106)
10.2.5Gapped Clocks (107)
10.3R ESET AND P OWER-D OWN (108)
10.4G LOBAL R ESOURCES (110)
10.4.1Clock Rate Adapter (CLAD) (110)
10.4.28 kHz Reference Generation (112)
10.4.3One Second Reference Generation (114)
10.4.4General-Purpose IO Pins (114)
10.4.5Performance Monitor Counter Update Details (115)
10.4.6Transmit Manual Error Insertion (116)
10.5P ER-P ORT R ESOURCES (117)
10.5.1Loopbacks (117)
10.5.2Loss Of Signal Propagation (119)
10.5.3AIS Logic (119)
10.5.4Loop Timing Mode (122)
10.5.5HDLC Overhead Controller (122)
10.5.6Trail Trace (122)
10.5.7BERT (122)
10.5.8Fractional Payload Controller (123)
10.5.9PLCP/Fractional port pins (123)
10.5.10Framing Modes (127)
10.5.11Mapping Modes (129)
10.5.12Line Interface Modes (133)
10.6UTOPIA/POS-PHY/SPI-3 S YSTEM I NTERFACE (135)
10.6.1General Description (135)
10.6.2Features (135)
10.6.6System Interface Bus Controller (136)
10.7ATM C ELL / HDLC P ACKET P ROCESSING (141)
10.7.1General Description (141)
10.7.2Features (141)
10.7.3Transmit Cell/Packet Processor (142)
10.7.4Receive Cell/Packet Processor (142)
DS3181/DS3182/DS3183/DS3184
10.7.6Packet Processor (148)
10.7.7FIFO (150)
10.7.8System Loopback (151)
10.8DS3/E3 PLCP F RAMER (153)
10.8.1General Description (153)
10.8.2Features (153)
10.8.3Transmit PLCP Frame Processor (154)
10.8.4Receive PLCP Frame Processor (154)
10.8.5Transmit DS3 PLCP Frame Processor (154)
10.8.6Receive DS3 PLCP Frame Processor (157)
10.8.7Transmit E3 PLCP Frame Processor (158)
10.8.8Receive E3 PLCP Frame Processor (161)
10.9F RACTIONAL P AYLOAD C ONTROLLER (163)
10.9.1General Description (163)
10.9.2Features (163)
10.9.3Transmit Fractional Interface (164)
10.9.4Transmit Fractional Controller (164)
10.9.5Receive Fractional Interface (164)
10.9.6Receive Fractional Controller (164)
10.10DS3/E3 F RAMER / F ORMATTER (166)
10.10.1General Description (166)
10.10.2Features (166)
10.10.3Transmit Formatter (167)
10.10.4Receive Framer (167)
10.10.5C-bit DS3 Framer/Formatter (171)
10.10.6M23 DS3 Framer/Formatter (174)
10.10.7G.751 E3 Framer/Formatter (177)
10.10.8G.832 E3 Framer/Formatter (179)
10.10.9Clear-Channel Frame Processor (184)
10.11HDLC O VERHEAD C ONTROLLER (184)
10.11.1General Description (184)
10.11.2Features (185)
10.11.3Transmit FIFO (185)
10.11.4Transmit HDLC Overhead Processor (186)
10.11.5Receive HDLC Overhead Processor (186)
10.11.6Receive FIFO (187)
10.12T RAIL T RACE C ONTROLLER (187)
10.12.1General Description (187)
10.12.2Features (188)
10.12.3Functional Description (189)
10.12.4Transmit Data Storage (189)
10.12.5Transmit Trace ID Processor (189)
10.12.6Transmit Trail Trace Processing (189)
10.12.7Receive Trace ID Processor (189)
10.12.8Receive Trail Trace Processing (189)
10.12.9Receive Data Storage (190)
10.13FEAC C ONTROLLER (191)
10.13.1General Description (191)
10.13.2Features (191)
10.13.3Functional Description (191)
10.14L INE E NCODER/D ECODER (193)
10.14.1General Description (193)
10.14.2Features (193)
10.14.3B3ZS/HDB3 Encoder (193)
10.14.4Transmit Line Interface (194)
10.14.5Receive Line Interface (194)
10.14.6B3ZS/HDB3 Decoder (194)
DS3181/DS3182/DS3183/DS3184
10.15.1General Description (196)
10.15.2Features (196)
10.15.3Configuration and Monitoring (196)
10.15.4Receive Pattern Detection (197)
10.15.5Transmit Pattern Generation (199)
10.16LIU – L INE I NTERFACE U NIT (200)
10.16.1General Description (200)
10.16.2Features (200)
10.16.3Detailed Description (201)
10.16.4Transmitter (201)
10.16.5Receiver (202)
11OVERALL REGISTER MAP 205 12REGISTER MAPS AND DESCRIPTIONS 208
12.1R EGISTERS B IT M APS (208)
12.1.1Global Register Bit Map (208)
12.1.2HDLC Register Bit Map (211)
12.1.3T3 Register Bit Map (213)
12.1.4E3 G.751 Register Bit Map (214)
12.1.5E3 G.832 Register Bit Map (214)
12.1.6Clear-Channel Register Bit Map (215)
12.1.7Fractional Register Bit Map (216)
12.1.8Transmit Cell Processor Bit Map (218)
12.1.9Transmit Packet Processor Bit Map (219)
12.2G LOBAL R EGISTERS (221)
12.2.1Register Bit Descriptions (222)
12.3UTOPIA/POS-PHY S YSTEM I NTERFACE (230)
12.3.1Transmit System Interface (230)
12.3.2Receive System Interface Register Map (231)
12.4P ER-P ORT C OMMON (234)
12.4.1Register Bit Descriptions (234)
12.5BERT (247)
12.5.1BERT Register Map (247)
12.5.2BERT Register Bit Descriptions (247)
12.6B3ZS/HDB3 L INE E NCODER/D ECODER (254)
12.6.1Transmit Side Line Encoder/Decoder Register Map (254)
12.6.2Receive Side Line Encoder/Decoder Register Map (255)
12.7HDLC (259)
12.7.1HDLC Transmit Side Register Map (259)
12.7.2HDLC Receive Side Register Map (262)
12.8FEAC C ONTROLLER (266)
12.8.1FEAC Transmit Side Register Map (266)
12.8.2FEAC Receive Side Register Map (268)
12.9T RAIL T RACE (271)
12.9.1Trail Trace Transmit Side (271)
12.9.2Trail Trace Receive Side Register Map (272)
12.10DS3/E3 F RAMER (277)
12.10.1Transmit DS3 (277)
12.10.2Receive DS3 Register Map (279)
12.10.3Transmit G.751 E3 (287)
12.10.4Receive G.751 E3 Register Map (289)
12.10.5Transmit G.832 E3 Register Map (293)
12.10.6Receive G.832 E3 Register Map (297)
12.10.7Transmit Clear Channel (305)
12.10.8Receive Clear Channel (306)
12.11F RACTIONAL DS3/E3 (308)
12.11.1Fractional Transmit Side Register Map (308)
DS3181/DS3182/DS3183/DS3184
12.12DS3/E3 PLCP (311)
12.12.1Transmit Side PLCP (311)
12.12.2Receive Side PLCP Register Map (315)
12.13FIFO R EGISTERS (323)
12.13.1Transmit FIFO Register Map (323)
12.13.2Receive FIFO Register Map (326)
12.14C ELL/P ACKET P ROCESSOR (328)
12.14.1Transmit Cell Processor Register Map (328)
12.14.2Receive Cell Processor (335)
12.14.3Transmit Packet Processor Register Map (345)
12.14.4Receive Packet Processor Register Map (350)
13JTAG INFORMATION 359
13.1JTAG D ESCRIPTION (359)
13.2JTAG TAP C ONTROLLER S TATE M ACHINE D ESCRIPTION (359)
13.3JTAG I NSTRUCTION R EGISTER AND I NSTRUCTIONS (361)
13.4JTAG ID C ODES (363)
13.5JTAG F UNCTIONAL T IMING (363)
13.6IO P INS (363)
14PIN ASSIGNMENT 364 15PACKAGE MECHANICAL DIMENSIONS 367 16PACKAGE THERMAL INFORMATION 370 17DC ELECTRICAL CHARACTERISTICS 371 18AC TIMING CHARACTERISTICS 373
18.1F RACTIONAL P ORT C HARACTERISTICS (375)
18.2L INE I NTERFACE AC C HARACTERISTICS (375)
18.3M ISCELLANEOUS P IN AC C HARACTERISTICS (376)
18.4O VERHEAD P ORT AC C HARACTERISTICS (376)
18.5S YSTEM I NTERFACE AC C HARACTERISTICS (377)
18.6M ICRO I NTERFACE AC C HARACTERISTICS (379)
18.7CLAD J ITTER C HARACTERISTICS (382)
18.8LIU I NTERFACE AC C HARACTERISTICS (382)
18.8.1Waveform Templates (382)
18.8.2LIU Input/Output Characteristics (386)
18.9JTAG I NTERFACE AC C HARACTERISTICS (388)
19REVISION HISTORY 389
DS3181/DS3182/DS3183/DS3184
LIST OF FIGURES
Figure 1-1. LIU External Connections For A DS3/E3/STS-1 Port of a DS318x Device (14)
Figure 1-2. DS318x Functional Block Diagram (14)
Figure 2-1. Four-Port Unchannelized ATM over DS3/E3/CC52 Line Card (15)
Figure 2-2. Four-Port Unchannelized HDLC over DS3/E3/CC52 Line Card (16)
Figure 6-1. DS3/E3 ATM/Packet Mode (26)
Figure 6-2. DS3/E3 ATM/Packet—OHM Mode (27)
Figure 6-3. DS3/E3 Internal Fractional ATM/Packet Mode (28)
Figure 6-4. DS3/E3 External Fractional ATM/Packet Mode (29)
Figure 6-5. DS3/E3 Flexible External Fractional Mode (30)
Figure 6-6. DS3/E3 G.751 PLCP ATM Mode (31)
Figure 6-7. DS3/E3 G.751 PLCP ATM—OHM Mode (33)
Figure 6-8. Clear-Channel ATM/Packet Modes (34)
Figure 6-9. Clear-Channel ATM/Packet—OHM Mode (35)
Figure 6-10. Clear-Channel Octet Aligned ATM/Packet—OHM Mode (36)
Figure 7-1. HDB3/B3ZS/AMI LIU Mode (38)
Figure 7-2. HDB3/B3ZS/AMI Non-LIU Line Interface Mode (39)
Figure 7-3. UNI Line Interface Mode (40)
Figure 7-4. UNI Line Interface—OHM Mode (41)
Figure 8-1. TX Line IO B3ZS Functional Timing Diagram (66)
Figure 8-2. TX Line IO HDB3 Functional Timing Diagram (67)
Figure 8-3. RX Line IO B3ZS Functional Timing Diagram (67)
Figure 8-4. RX Line IO HDB3 Functional Timing Diagram (68)
Figure 8-5. TX Line IO UNI OHM Functional Timing Diagram (68)
Figure 8-6. TX Line IO UNI Octet Aligned OHM Functional Timing Diagram (68)
Figure 8-7. RX Line IO OHM UNI Functional Timing Diagram (69)
Figure 8-8. RX Line IO UNI Octet Aligned OHM Functional Timing Diagram (69)
Figure 8-9. DS3 Framing Receive Overhead Port Timing (69)
Figure 8-10. E3 G.751 Framing Receive Overhead Port Timing (70)
Figure 8-11. E3 G.832 Framing Receive Overhead Port Timing (70)
Figure 8-12. DS3 Framing Transmit Overhead Port Timing (70)
Figure 8-13. E3 G.751 Framing Transmit Overhead Port Timing (70)
Figure 8-14. E3 G.832 Framing Transmit Overhead Port Timing (71)
Figure 8-15. DS3 PLCP Receive Overhead Port Timing (71)
Figure 8-16. E3 G.751 PLCP Receive Overhead Port Timing (71)
Figure 8-17. DS3 PLCP Transmit Overhead Port Timing (71)
Figure 8-18. E3 G.751 PLCP Transmit Overhead Port Timing (72)
Figure 8-19. External (XFRAC) Transmit Fractional Timing (72)
Figure 8-20. External (XFRAC) Receive Fractional Timing (72)
Figure 8-21. Internal (IFRAC) Transmit Fractional Timing (73)
Figure 8-22. Internal (IFRAC) Receive Fractional Timing (73)
Figure 8-23. Transmit Flexible Fractional (FFRAC) Timing (74)
Figure 8-24. Receive Flexible Fractional (FFRAC) Timing (74)
Figure 8-25. UTOPIA Level 2 Transmit Cell Transfer Direct Mode (75)
Figure 8-26. UTOPIA Level 2 Receive Cell Transfer Direct Mode (76)
Figure 8-27. UTOPIA Level 2 Transmit Multiple Cell Transfer Polled Mode (77)
Figure 8-28. UTOPIA Level 2 Receive Multiple Cell Transfer Polled Mode (77)
Figure 8-29. UTOPIA Level 2 Receive Unexpected Multiple Cell Transfer (78)
Figure 8-30. UTOPIA Level 3 Transmit Multiple Cell Transfer Direct Mode (79)
Figure 8-31. UTOPIA Level 3 Transmit Multiple Cell Transfer Polled Mode (80)
Figure 8-32. UTOPIA Level 3 Receive Multiple Cell Transfer Direct Mode (81)
Figure 8-33. UTOPIA Level 3 Receive Multiple Cell Transfer Polled Mode (81)
Figure 8-34. Transmit Multiple Packet Transfer to Different PHY ports (direct status mode) (82)
Figure 8-35. POS-PHY Level 2 Receive Multiple Packet Transfer from Different PHY Ports/Devices (direct status mode) (83)
Figure 8-36. POS-PHY Level 2 Transmit Multiple Packet Transfer to Different PHY Ports (polled status mode) (84)
DS3181/DS3182/DS3183/DS3184 Figure 8-38. POS-PHY Level 3 Transmit Multiple Packet Transfer In-Band Addressing (86)
Figure 8-39. POS-PHY Level 3 Receive Multiple Packet Transfer In-Band Addressing (87)
Figure 8-40. 16-Bit Mode Write (88)
Figure 8-41. 16-Bit Mode Read (88)
Figure 8-42. 8-Bit Mode Write (89)
Figure 8-43. 8-Bit Mode Read (89)
Figure 8-44. 16-Bit Mode without Byte Swap (90)
Figure 8-45. 16-Bit Mode with Byte Swap (90)
Figure 8-46. Clear Status Latched Register on Read (91)
Figure 8-47. Clear Status Latched Register on Write (91)
Figure 8-48. RDY Signal Functional Timing Writes (92)
Figure 8-49. RDY Signal Functional Timing Read (92)
Figure 10-1. Interrupt Structure (99)
Figure 10-2. Internal TX Clock (102)
Figure 10-3. Internal RX Clock (103)
Figure 10-4. Example IO Pin Clock Muxing (107)
Figure 10-5. Reset Sources (108)
Figure 10-6. CLAD Block (111)
Figure 10-7. 8KREF Logic (113)
Figure 10-8. Performance Monitor Update Logic (116)
Figure 10-9. Transmit Error Insert Logic (117)
Figure 10-10. Loopback Modes (118)
Figure 10-11. ALB Mux (118)
Figure 10-12. AIS Signal Flow (121)
Figure 10-13. DS3 C-Bit or DS3 M23 (with C-Bit Generation) Frame (129)
Figure 10-14. DS3 PLCP Frame (130)
Figure 10-15. DS3 M23 (with C-bits used as payload) Frame (131)
Figure 10-16. E3 G.751 Frame (131)
Figure 10-17. E3 PLCP Frame (132)
Figure 10-18. Example E3 G.751 Internal Fractional Frame (132)
Figure 10-19. E3 G.832 Frame (133)
Figure 10-20. System Interface Functional Diagram (135)
Figure 10-21. Normal Packet Format in 32-Bit Mode (136)
Figure 10-22. Normal Packet Format in 16-Bit Mode (136)
Figure 10-23. Byte Reordered Packet Format in 32-Bit Mode (136)
Figure 10-24. Byte Reordered Packet Format in 16-Bit Mode (137)
Figure 10-25. ATM Cell/HDLC Packet Functional Diagram (141)
Figure 10-26. Receive DSS Scrambler Synchronization State Diagram (145)
Figure 10-27. Cell Delineation State Diagram (146)
Figure 10-28. HEC Error Monitoring State Diagram (147)
Figure 10-29. Cell Format for 53-Byte Cell With 32-Bit Data Bus (147)
Figure 10-30. Cell Format for 52-Byte Cell With 32-Bit Data Bus (148)
Figure 10-31. PLCP Framer Functional Diagram (153)
Figure 10-32. DS3 PLCP Frame Format (154)
Figure 10-33. DS3 PLCP G1 Byte Format (155)
Figure 10-34. E3 PLCP Frame Format (159)
Figure 10-35. E3 PLCP G1 Byte Format (159)
Figure 10-36. Fractional Payload Controller Detailed Block Diagram (163)
Figure 10-37. Data Group Format (165)
Figure 10-38. Frame Format (165)
Figure 10-39. Framer Detailed Block Diagram (166)
Figure 10-40. DS3 Frame Format (168)
Figure 10-41. DS3 Subframe Framer State Diagram (169)
Figure 10-42. DS3 Multiframe Framer State Diagram (170)
Figure 10-43. G.751 E3 Frame Format (177)
Figure 10-44. G.832 E3 Frame Format (179)
Figure 10-45. MA Byte Format (180)
DS3181/DS3182/DS3183/DS3184 Figure 10-47. Trail Trace Controller Block Diagram (188)
Figure 10-48. Trail Trace Byte (DT = Trail Trace Data) (190)
Figure 10-49. FEAC Controller Block Diagram (191)
Figure 10-50. FEAC Codeword Format (192)
Figure 10-51. Line Encoder/Decoder Block Diagram (193)
Figure 10-52. B3ZS Signatures (195)
Figure 10-53. HDB3 Signatures (195)
Figure 10-54. BERT Block Diagram (196)
Figure 10-55. PRBS Synchronization State Diagram (198)
Figure 10-56. Repetitive Pattern Synchronization State Diagram (199)
Figure 10-57. LIU Functional Diagram (200)
Figure 10-58. DS3/E3/STS-1 LIU Block Diagram (201)
Figure 10-59. Receiver Jitter Tolerance (204)
Figure 13-1. JTAG Block Diagram (359)
Figure 13-2. JTAG TAP Controller State Machine (360)
Figure 13-3. JTAG Functional Timing (363)
Figure 14-1. DS3184 Pin Assignments—400-Lead BGA (364)
Figure 14-2. DS3183 Pin Assignments—400-Lead BGA (365)
Figure 14-3. DS3182 Pin Assignments—400-Lead BGA (365)
Figure 14-4. DS3181 Pin Assignments—400-Lead BGA (366)
Figure 15-1. Mechanical Dimensions—400-Lead BGA (367)
Figure 15-2. Mechanical Dimensions (continued) (369)
Figure 18-1. Clock Period and Duty Cycle Definitions (373)
Figure 18-2. Rise Time, Fall Time, and Jitter Definitions (373)
Figure 18-3. Hold, Setup, and Delay Definitions (Rising Clock Edge) (373)
Figure 18-4. Hold, Setup, and Delay Definitions (Falling Clock Edge) (374)
Figure 18-5. To/From High-Z Delay Definitions (Rising Clock Edge) (374)
Figure 18-6. To/From High-Z Delay Definitions (Falling Clock Edge) (374)
Figure 18-7. Micro Interface Nonmultiplexed Read/Write Cycle (380)
Figure 18-8. Micro Interface Multiplexed Read Cycle (381)
Figure 18-9. E3 Waveform Template (384)
Figure 18-10. STS-1 Pulse Mask Template (385)
Figure 18-11. DS3 Pulse Mask Template (386)
DS3181/DS3182/DS3183/DS3184
LIST OF TABLES
Table 4-1. Standards Compliance (23)
Table 6-1. DS3/E3 ATM/Packet Mode Configuration Registers (26)
Table 6-2. DS3/E3 ATM/Packet—OHM Mode Configuration Registers (27)
Table 6-3. DS3/E3 Internal Fractional (IFRAC) ATM/Packet Mode Configuration Registers (28)
Table 6-4. DS3/E3 External Fractional (XFRAC) ATM/Packet Mode Configuration Registers (29)
Table 6-5. DS3/E3 Flexible External Fractional (Subrate) Mode Configuration Registers (30)
Table 6-6. DS3/E3 G.751 PLCP ATM Mode Configuration Registers (31)
Table 6-7. DS3/E3 G.751 PLCP ATM—OHM Mode Configuration Registers (32)
Table 6-8. Clear-Channel ATM/Packet Mode Configuration Modes (34)
Table 6-9. Clear-Channel ATM/Packet—OHM Mode Configuration Registers (35)
Table 6-10. Clear-Channel Octet Aligned ATM/Packet—OHM Mode Configuration Registers (36)
Table 7-1. HDB3/B3ZS/AMI LIU Mode Configuration Registers (37)
Table 7-2. HDB3/B3ZS/AMI Non-LIU Mode Configuration Registers (39)
Table 7-3. UNI Line Interface Mode Configuration Registers (40)
Table 7-4. UNI Line Interface—OHM Mode Configuration Registers (41)
Table 8-1. DS3184 Short Pin Descriptions (42)
Table 8-2. Detailed Pin Descriptions (47)
Table 9-1. Configuration of Global Register Settings (94)
Table 9-2. Configuration of Port Register Settings (94)
Table 10-1. LIU Enable Table (101)
Table 10-2. All Possible Clock Sources Based on Mode and Loopback (101)
Table 10-3. Source Selection of TLCLK Clock Signal (102)
Table 10-4. Source Selection of TCLKOn (internal TX clock) (103)
Table 10-5. Source Selection of RCLKO Clock Signal (internal RX clock) (103)
Table 10-6. Transmit Line Interface Signal Pin Valid Timing Source Select (104)
Table 10-7. Transmit Framer Pin Signal Timing Source Select (105)
Table 10-8. Receive Line Interface Pin Signal Timing Source Select (105)
Table 10-9. Receive Framer Pin Signal Timing Source Select (106)
Table 10-10. Reset and Power-Down Sources (109)
Table 10-11. CLAD IO Pin Decode (112)
Table 10-12. Global 8 kHz Reference Source Table (113)
Table 10-13. Port 8 kHz Reference Source Table (113)
Table 10-14. GPIO Global Signals (114)
Table 10-15. GPIO Pin Global Mode Select Bits (114)
Table 10-16. GPIO Port Alarm Monitor Select (115)
Table 10-17. Loopback Mode Selections (117)
Table 10-18. Line AIS Enable Modes (121)
Table 10-19. Payload (downstream) AIS Enable Modes (122)
Table 10-20. TSOFIn/TOHMIn Input Pin Functions (123)
Table 10-21. TSERn/TPOHn/TFOHn Input Pin Functions (123)
Table 10-22. TPDENIn/TPOHENn/TFOHENIn Input Pin Functions (124)
Table 10-23. TSOFOn/TDENn/TPOHSOFn/TFOHENOn Output Pin Functions (124)
Table 10-24. TCLKOn/TGCLKn/TPOHCLKn Output Pin Functions (125)
Table 10-25. TPDATn Input Pin Functions (125)
Table 10-26. TPDENOn Output Pin Functions (125)
Table 10-27. RSERn/RPOHn Output Pin Functions (126)
Table 10-28. RPDENIn / RFOHENIn Input Pin Functions (126)
Table 10-29. RPDATn Input Pin Functions (126)
Table 10-30. RSOFOn/RDENn/RPOHSOFn/RFOHENOn Output Pin Functions (127)
Table 10-31. RCLKOn/RGCLKn/RPOHCLKn Output Pin Functions (127)
Table 10-32. Framing Mode Select Bits FM[5:0] (128)
Table 10-33. Line Mode Select Bits LM[2:0] (134)
Table 10-34. C-bit DS3 Frame Overhead Bit Definitions (172)
Table 10-35. M23 DS3 Frame Overhead Bit Definitions (175)
Table 10-36. G.832 E3 Frame Overhead Bit Definitions (180)
DS3181/DS3182/DS3183/DS3184 Table 10-38. Pseudorandom Pattern Generation (197)
Table 10-39. Repetitive Pattern Generation (197)
Table 10-40. Transformer Characteristics (202)
Table 10-41. Recommended Transformers (203)
Table 11-1. Global and Test Register Address Map (206)
Table 11-2. Per-Port Register Address Map (206)
Table 12-1. Global Register Bit Map (208)
Table 12-2. System Interface Bit Map (208)
Table 12-3. Port Register Bit Map (209)
Table 12-4. BERT Register Bit Map (210)
Table 12-5. LINE Register Bit Map (210)
Table 12-6. HDLC Register Bit Map (211)
Table 12-7. FEAC Register Bit Map (211)
Table 12-8. Trail Trace Register Bit Map (212)
Table 12-9. T3 Register Bit Map (213)
Table 12-10. E3 G.751 Register Bit Map (214)
Table 12-11. E3 G.832 Register Bit Map (214)
Table 12-12. Clear-Channel Register Bit Map (215)
Table 12-13. Fractional Register Bit Map (216)
Table 12-14. PLCP Register Bit Map (216)
Table 12-15. FIFO Register Bit Map (217)
Table 12-16. Transmit Cell Processor Register Bit Map (218)
Table 12-17. Transmit Packet Processor Register Bit Map (219)
Table 12-18. Receive Cell Processor Register Bit Map (219)
Table 12-19. Receive Packet Processor Register Bit Map (220)
Table 12-20. Global Register Map (221)
Table 12-21. Transmit System Interface Register Map (230)
Table 12-22. Receive System Interface Register Map (231)
Table 12-23. Per-Port Common Register Map (234)
Table 12-24. BERT Register Map (247)
Table 12-25. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map (254)
Table 12-26. Receive Side B3ZS/HDB3 Line Encoder/Decoder Register Map (255)
Table 12-27. Transmit Side HDLC Register Map (259)
Table 12-28. Receive Side HDLC Register Map (262)
Table 12-29. FEAC Transmit Side Register Map (266)
Table 12-30. FEAC Receive Side Register Map (268)
Table 12-31. Transmit Side Trail Trace Register Map (271)
Table 12-32. Trail Trace Receive Side Register Map (272)
Table 12-33. Transmit DS3 Framer Register Map (277)
Table 12-34. Receive DS3 Framer Register Map (279)
Table 12-35. Transmit G.751 E3 Framer Register Map (287)
Table 12-36. Receive G.751 E3 Framer Register Map (289)
Table 12-37. Transmit G.832 E3 Framer Register Map (293)
Table 12-38. Receive G.832 E3 Framer Register Map (297)
Table 12-39. Transmit Clear-Channel Register Map (305)
Table 12-40. Receive Clear-Channel Register Map (306)
Table 12-41. Fractional Transmit Side Register Map (308)
Table 12-42. Receive Side Register Map (309)
Table 12-43. Transmit Side PLCP Register Map (311)
Table 12-44. Receive Side PLCP Register Map (315)
Table 12-45. Transmit FIFO Register Map (323)
Table 12-46. Receive FIFO Register Map (326)
Table 12-47. Transmit Cell Processor Register Map (328)
Table 12-48. HEC Error Mask (331)
Table 12-49. Receive Cell Processor Register Map (335)
Table 12-50. Transmit Packet Processor Register Map (345)
Table 12-51. Receive Packet Processor Register Map (350)
DS3181/DS3182/DS3183/DS3184 Table 13-2. JTAG ID Codes (363)
Table 14-1. Pin Assignment Breakdown (364)
Table 17-1. Recommended DC Operating Conditions (371)
Table 17-2. DC Electrical Characteristics (371)
Table 17-3. Output Pin Drive (372)
Table 18-1. Fractional Port Timing (375)
Table 18-2. Line Interface Timing (375)
Table 18-3. Miscellaneous Pin Timing (376)
Table 18-4. Overhead Port Timing (376)
Table 18-5. System Interface L2 Timing (377)
Table 18-6. System Interface L3 Timing (378)
Table 18-7. Micro Interface Timing (379)
Table 18-8. DS3 Waveform Template (382)
Table 18-9. DS3 Waveform Test Parameters and Limits (382)
Table 18-10. STS-1 Waveform Template (383)
Table 18-11. STS-1 Waveform Test Parameters and Limits (383)
Table 18-12. E3 Waveform Test Parameters and Limits (384)
Table 18-13. Receiver Input Characteristics—DS3 and CC52 Modes (386)
Table 18-14. Receiver Input Characteristics—E3 Mode (387)
Table 18-15. Transmitter Output Characteristics—DS3 and STS-1 Modes (387)
Table 18-16. Transmitter Output Characteristics—E3 Mode (387)
Table 18-17. JTAG Interface Timing (388)
DS3181/DS3182/DS3183/DS3184
1 BLOCK DIAGRAMS
Figure 1-1 shows the external components required at each LIU interface for proper operation. Figure 1-2 shows the functional block diagram of one channel ATM/Packet PHY.
Figure 1-1. LIU External Connections For A DS3/E3/STS-1 Port of a DS318x Device
DS3181/DS3182/DS3183/DS3184
2 APPLICATIONS
· Access Concentrators
· Multiservice Access Platforms
· ATM and Frame Relay Equipment
· Routers and Switches
· SONET/SDH ADM
· SONET/SDH Muxes
· PBXs
· Digital Cross Connect
· PDH Multiplexer/Demultiplexer
· Test Equipment
· Integrated Access Device (IAD)
Figure 2-1 and Figure 2-2 show applications for the DS3184 as four-port unchannelized ATM and packet DS3/E3 line cards, respectively.
Figure 2-1. Four-Port Unchannelized ATM over DS3/E3/CC52 Line Card
DS3181/DS3182/DS3183/DS3184 Figure 2-2. Four-Port Unchannelized HDLC over DS3/E3/CC52 Line Card
DS3181/DS3182/DS3183/DS3184
3 FEATURE DETAILS
The following sections describe the features provided by the DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs.
3.1 Global Features
· System interface configurable for UTOPIA L2/UTOPIA L3 for ATM cell traffic or POS-PHY L2/POS-PHY L3 or SPI-3 for HDLC packets or mixed packet/cell traffic
· Supports the following transmission protocols:
· Direct-mapped ATM over DS3 or sub-rate DS3
· PLCP-mapped ATM over DS3
· Direct-mapped ATM over G.751 E3 or sub-rate G.751 E3
· PLCP-mapped ATM over G.751 E3
· Direct-mapped ATM over G.832 E3 or sub-rate G.832 E3
· Bit or byte synchronous (octet aligned) direct-mapped ATM over externally-defined frame formats up to
52 Mbps
· Clear-channel ATM (cell-based physical layer) at line rates up to 52 Mbps
· Clear-channel ATM DSS at line rates up to 52 Mbps
· Direct-mapped HDLC over DS3 or sub-rate DS3
· Direct-mapped HDLC over G.751 E3 or sub-rate G.751 E3
· Direct-mapped HDLC over G.832 E3 or sub-rate G.832 E3
· Bit or byte synchronous (octet aligned) direct-mapped HDLC over externally-defined frame formats up to 52 Mbps
· Clear-channel HDLC at line rates up to 52 Mbps
· In UTOPIA bus mode, ports are independently configurable for any ATM protocol
· In POS-PHY bus mode, ports are independently configurable for any ATM or HDLC protocol
· Programmable to support internally or externally controlled sub-rate DS3 or E3 on any ports
· Supports gapped 52 MHz clock rates for signals embedded in SONET/SDH
· Optional transmit loop timed clock(s) mode using the associated port’s receive clock(s)
· Optional transmit clock mode using references generated by the internal Clock Rate Adapter (CLAD)
· Requires only a single reference clock for all three LIU data rates using internal CLAD
· The LIU can be powered down and bypassed for direct logic IO to/from line circuits.
· Jitter attenuator can be placed in either transmit or receive path when the LIU is enabled.
· Clock, data and control signals can be inverted for a direct interface to many other devices
· Detection of loss of transmit clock and loss of receive clock
· Automatic one-second, external or manual update of performance monitoring counters
· Each port can be placed into a low-power standby mode when not being used
· Framing and line code error insertion available
3.2 Receive DS3/E3/STS-1 LIU Features
· AGC/Equalizer block handles from 0 dB to 15 dB of cable loss
· Loss-of-lock PLL status indication
· Interfaces directly to a DSX monitor signal (20 dB flat loss) using built-in pre-amp
· Digital and analog Loss of Signal (LOS) detectors (ANSI T1.231 and ITU G.775)
· Per-channel power-down control
3.3 Receive DS3/E3 Framer Features
· Frame synchronization for M23 or C-bit Parity DS3, or G.751 E3 or G.832 E3
· B3ZS/HDB3/AMI decoding
· Detection and accumulation of bipolar violations (BPV), code violations (CV), excessive zeroes occurrences (EXZ), F-bit errors, M-bit errors, FAS errors, LOF occurrences, P-bit parity errors, CP-bit parity errors, BIP-8
DS3181/DS3182/DS3183/DS3184 · Detection of RDI, AIS, DS3 idle signal, loss of signal (LOS), severely errored framing event (SEFE), change of frame alignment (COFA), receipt of B3ZS/HDB3 code words, DS3 application ID bit, DS3 M23/C-bit format mismatch, G.751 national bit, and G.832 RDI (FERF), payload type, and timing marker bits
· HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
· FEAC port for DS3 FEAC channel
· 16-byte Trail Trace Buffer port for G.832 trail access point identifier
· DS3 M23 C bits and stuff bits configurable as payload or overhead, stored in registers for software inspection · Most framing overhead fields presented on the receive overhead port
· Support for internal and external subrate DS3/E3 control (Fractional DS3/E3)
3.4 Receive PLCP Framer Features
· PLCP frame synchronization
· C1 cycle/stuff counter interpretation
· Detection of out of frame (OOF), BIP-8 errors, FEBE and RAI (Yellow Signal)
· Frame timing can be presented on the GPIO2 output pin or used as the transmit PLCP reference
· All path overhead fields presented on the PLCP receive overhead port
· HDLC port for data link messages on F1, M1 or M2 bytes
· Trail Trace port for trace messages on F1 byte
3.5 Receive Cell Processor Features
· HEC-based cell delineation within the DS3/E3 frame, the PLCP frame, an externally defined frame, or the entire line bandwidth
· Cell descrambling using the self-synchronizing scrambler (x43+1) for ATM over DS3/E3
· Distributed Sample Scrambler (DSS) for clear-channel ATM (cell-based physical layer)
· HEC error detection and correction; HEC discard
· Filtering of idle, unassigned and/or invalid cells (provisionable)
· Header pattern comparison vs. 32-bit header pattern and mask registers; counting of matching or non-matching cells; discard of matching or non-matching cells
· Four-cell Receive FIFO
· Controls include enables/disables/settings for: cell processing, coset polynomial addition, error correction, erred cell extraction, cell descrambling, idle/unassigned/invalid cell filtering, header pattern match counting/discarding, LCD integration time
· Status fields include: out of cell delineation (OCD), loss of cell delineation (LCD) and receipt of idle, unassigned, invalid, erred, corrected or header-pattern-match cells
· Performance monitoring counters for forwarded cells, corrected cells, uncorrectable cells, header pattern match/no-match cells, and filtered idle/unassigned/invalid cells
· Octet alignment option for externally defined frame formats
3.6 Receive Packet Processor Features
· Packet descrambling using the self-synchronizing scrambler (x43+1)
· Flag detection, packet delineation, and inter-frame fill discard (flags and all-ones)
· Packet abort detection and accumulation
· Bit or octet destuffing
· FCS checking (16-bit or 32-bit), error accumulation, and FCS discard
· Packet size checking vs. programmable minimum and maximum size registers
· Abort declaration for packets with non-integral number of bytes
· Controls include enables/disables/settings for: packet processing, descrambling, 16/32-bit FCS, filtering of FCS erred packets, FCS discard, minimum/maximum packet size
· Status fields include: receipt of FCS erred packet, aborted packet, size violation packet, non-integer-length packets
· Performance monitoring counters for forwarded packets, forwarded bytes, aborted bytes, FCS erred packets, aborted packets, size violation packets (min, max, non-integer-length)
· Octet alignment with octet destuffing option for externally defined frame formats
DS3181/DS3182/DS3183/DS3184
3.7 Receive FIFO Features
· Storage capacity for four cells or 256 bytes of packet data per port
· Programmable port address
· Programmable fill level thresholds
· Underflow and overflow status indications
3.8 Receive System Interface Features
· UTOPIA L2 / UTOPIA L3 interface in cell mode, POS-PHY L2 / POS-PHY L3 or SPI-3 interface in packet or mixed traffic modes
· 8, 16, or 32-bit data bus at clock rates from 10 MHz to 66 MHz (52 MHz in L2 modes)
· Polled and direct cell available outputs
· Controls include enables/disables/settings for: HEC transfer, signal inversions, parity enable/polarity, cell available deassertion time
3.9 Transmit System Interface Features
· UTOPIA L2 / UTOPIA L3 interface in cell mode, POS-PHY L2 / POS-PHY L3 or SPI-3 interface in packet or mixed traffic modes
· 8, 16, or 32-bit data bus at clock rates from 10 MHz to 66 MHz (52 MHz in L2 modes)
· Polled and direct cell available outputs
· Controls include enables/disables/settings for: HEC transfer, signal inversions, parity enable/polarity, cell available deassertion time
3.10 Transmit FIFO Features
· Storage capacity for four cells or 256 bytes of packet data per port
· Programmable port address
· Programmable fill level thresholds
· Underflow and overflow status indications
3.11 Transmit Cell Processor Features
· Programmable fill cell type
· HEC calculation and insertion/overwrite, including coset addition
· Cell scrambling using the self-synchronizing scrambler (x43+1) for ATM over DS3/E3
· Distributed Sample Scrambler (DSS) for clear-channel ATM (cell-based physical layer)
· Single-bit and multiple-bit header error insertion for diagnostics
· Controls include enables/disables/settings for: cell processing, HEC insertion, coset polynomial addition, cell scrambling, fill cell type, error insertion type/rate/count, HEC bit corruption
· Counter for number of cells read from the transmit FIFO
· Cell mapping into the DS3/E3 frame, the PLCP frame, an externally defined frame, or the entire line bandwidth · Octet alignment option for externally defined frame formats
3.12 Transmit Packet Processor Features
· FCS calculation (16-bit or 32-bit) and insertion/overwrite
· Programmable FCS error insertion for diagnostics
· Bit or octet stuffing
· Programmable inter-frame fill insertion (flags or all-ones)
· Automatic packet abort insertion
· Packet scrambling using the self-synchronizing scrambler (x43+1)
· Controls include enables/disables/settings for: packet processing, FCS insertion or overwrite, 16/32-bit FCS, inter-frame fill type/length, scrambling, FCS error insertion type/rate/count
· Counters for number of packets and bytes read from the transmit FIFO
· Octet alignment with octet stuffing option for externally defined frame formats
DS3181/DS3182/DS3183/DS3184
3.13 Transmit PLCP Formatter Features
· Insertion of FAS bytes (A1, A2), path overhead identification (POI) bytes, and path overhead bytes
· Generation of BIP-8 (B1), FEBE and RAI (G1)
· C1 cycle/stuff counter generation referenced to GPIO4 input pin, referenced to the received PLCP timing, or based on an 8 kHz division of one of the clock sources
· Automatic or manual insertion of FAS errors, BIP-8 errors
· All path overhead fields can be sourced from the PLCP transmit overhead port
· HDLC port for data link messages on F1, M1 or M2 bytes
· Trail Trace port for trace messages on F1 byte
3.14 Transmit DS3/E3 Formatter Features
· Insertion of framing overhead for M23 or C-bit parity DS3, or G.751 E3 or G.832 E3
· B3ZS/HDB3 encoding
· Generation of RDI, AIS, and DS3 idle signal
· Automatic or manual insertion of bipolar violations (BPVs), excessive zeroes (EXZ) occurrences, F-bit errors, M-bit errors, FAS errors, P-bit parity errors, CP-bit parity errors, BIP-8 errors, and far end block errors (FEBE) · HDLC port for DS3 path maintenance data link (PMDL), G.751 national bit or G.832 NR or GC channels
· FEAC port for DS3 FEAC channel can be configured to send one codeword, one codeword continuously, or two different code words back-to-back to send DS3 Line Loopback commands
· 16-byte Trail Trace Buffer port for the G.832 trail access point identifier
· Insertion of G.832 payload type, and timing marker bits from registers
· DS3 M23 C bits configurable as payload or overhead; as overhead they can be controlled from registers or the transmit overhead port
· Most framing overhead fields can be sourced from transmit overhead port
· Formatter bypass mode for clear-channel or externally defined format applications
· Support for subrate DS3/E3, internally or externally controlled (Fractional DS3/E3)
3.15 Transmit DS3/E3/STS-1 LIU Features
· Wide 50+20% transmit clock duty cycle
· Line Build-Out (LBO) control
· Tri-state line driver outputs support protection switching applications
· Per-channel power-down control
· Output driver monitor status indication
3.16 Jitter Attenuator Features
· Fully integrated and requiring no external components
· Can be placed in transmit or receive path
· FIFO depth of 16 bits
· Standard compliant transmission jitter and wander
3.17 Clock Rate Adapter Features
· Generation of the internally needed DS3 (44.736 MHz), E3 (34.368 MHz), and STS-1 (51.84 MHz) clocks a from single input reference clock
· Input reference clock can be 51.84 MHz, 44.736MHz or 34.368 MHz
· Internally derived clocks can be used as references for LIU and jitter attenuator
· Derived clocks can be transmitted off-chip for external system use
· Standards compliant jitter and wander requirements.
3.18 HDLC Overhead Controller Features
· Each port has a dedicated HDLC controller for DS3/E3 framer or PLCP link management
· 256-byte receive and transmit FIFOs
· Handles all of the normal Layer 2 tasks including zero stuffing/destuffing, FCS generation/checking, abort