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MMA8452Q

Rev 3, 10/2010

Freescale Semiconductor Technical Data

An Energy Efficient Solution by Freescale

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

3-Axis, 12-bit/8-bit

Digital Accelerometer

The MMA8452Q is a smart low-power, three-axis, capacitive micromachined accelerometer with 12 bits of resolution. This accelerometer is packed with

embedded functions with flexible user programmable options, configurable to two interrupt pins. Embedded interrupt functions allow for overall power savings relieving the host processor from continuously polling data.

The MMA8452Q has user selectable full scales of ±2g/±4g/±8g with high pass filtered data as well as non filtered data available real-time. The device can be configured to generate inertial wake-up interrupt signals from any combination of the configurable embedded functions allowing the MMA8452Q to monitor events and remain in a low power mode during periods of inactivity . The MMA8452Q is available in a 3 mm x 3 mm x 1 mm QFN package. Features ? 1.95 V to 3.6 V supply voltage ? 1.6 V to 3.6 V interface voltage

?±2g/±4g/±8g dynamically selectable full-scale ?Output Data Rates (ODR) from 1.56 Hz to 800 Hz ?99 μg/√Hz noise

?12-bit and 8-bit digital output

?I 2C digital output interface (operates to 2.25 MHz with 4.7 k Ω pull-up)? 2 programmable interrupt pins for 6 interrupt sources ?

3 embedded channels of motion detection – Freefall or Motion Detection: 1 channel – Pulse Detection: 1 channel – Jolt Detection: 1 channel

?Orientation (Portrait/Landscape) detection with set hysteresis ?Automatic ODR change for Auto-WAKE and return to SLEEP ?High Pass Filter Data available real-time ?Self-T est

?RoHS compliant

Current Consumption: 6 μA – 165 μA

Typical Applications ?E-Compass applications

?Static orientation detection (Portrait/Landscape, Up/Down, Left/Right, Back/

Front position identification)

?Notebook, E-Reader and Laptop Tumble and Freefall Detection

?Real-time orientation detection (virtual reality and gaming 3D user position

feedback)

?Real-time activity analysis (pedometer step counting, freefall drop detection

for HDD, dead-reckoning GPS backup)

?Motion detection for portable product power saving (Auto-SLEEP and Auto-WAKE for cell phone, PDA, GPS, gaming)?Shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging)?User interface (menu scrolling by orientation change, tap detection for button replacement)

ORDERING INFORMATION

Part Number Temperature Range Package Description

Shipping MMA8452QT -40°C to +85°C QFN-16Tray MMA8452QR1

-40°C to +85°C

QFN-16

Tape and Reel

16 PIN QFN

3 mm x 3 mm x 1 mm

CASE 2077-01

MMA8452Q

MMA8452Q: 3-AXIS DIGITAL

ACCELEROMETER

±2g/±4g/±8g

Top and Bottom View

Contents

Application Notes for Reference (6)

1Block Diagram and Pin Description (6)

1.1Block Diagram (6)

Figure1. Block Diagram (6)

1.2Pin Description (6)

Figure2. Direction of the Detectable Accelerations (6)

Figure3. Landscape/Portrait Orientation (7)

Figure4. Application Diagram (7)

Table1. Pin Description (8)

1.3Soldering Information (8)

2Mechanical and Electrical Specifications (9)

2.1Mechanical Characteristics (9)

Table2. Mechanical Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted. (9)

2.2Electrical Characteristics (10)

Table3. Electrical Characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted. (10)

2.3I2C Interface Characteristic (11)

Table4. I2C Slave Timing Values (11)

Figure5. I2C Slave Timing Diagram (12)

2.4Absolute Maximum Ratings (12)

Table5. Maximum Ratings (12)

Table6. ESD and Latch-Up Protection Characteristics (12)

3Terminology (13)

3.1Sensitivity (13)

3.2Zero-g Offset (13)

3.3Self-Test (13)

4Modes of Operation (13)

Figure6. MMA8452Q Mode Transition Diagram (13)

Table7. Mode of Operation Description (13)

5Functionality (14)

5.1Device Calibration (14)

5.28-bit or 12-bit Data (14)

5.3Low Power Modes vs. High Resolution Modes (15)

5.4Auto-WAKE/SLEEP Mode (15)

5.5Freefall and Motion Detection (15)

5.5.1Freefall Detection (15)

5.5.2Motion Detection (15)

5.6Transient Detection (16)

5.7Tap Detection (16)

5.8Orientation Detection (16)

Figure7. Landscape/Portrait Orientation (16)

Figure8. Illustration of Landscape to Portrait Transition (17)

Figure9. Illustration of Portrait to Landscape Transition (17)

Figure10. Illustration of Z-Tilt Angle Lockout Transition (17)

5.9Interrupt Register Configurations (18)

Figure11. System Interrupt Generation Block Diagram (18)

5.10Serial I2C Interface (18)

Table8. Serial Interface Pin Description (18)

5.10.1I2C Operation (19)

Table9. I2C Address Selection Table (19)

Single Byte Read (19)

Multiple Byte Read (19)

Single Byte Write (19)

Multiple Byte Write (20)

Table10. I2C Device Address Sequence (20)

Figure12. I2C Timing Diagram (20)

MMA8452Q

Sensors

6Register Descriptions (21)

Table11. Register Address Map (21)

6.1Data Registers (22)

0X00 STATUS: Data Status Register (Read Only) (22)

Table12. STATUS Description (23)

Data Registers: 0x01 OUT_X_MSB, 0x02 OUT_X_LSB, 0x03 OUT_Y_MSB, 0X04 OUT_Y_LSB (24)

0x01 OUT_X_MSB: X_MSB Register (Read Only) (24)

0x02 OUT_X_LSB: X_LSB Register (Read Only) (24)

0x03 OUT_Y_MSB: Y_MSB Register (Read Only) (24)

0x04 OUT_Y_LSB: Y_LSB Register (Read Only) (24)

0x05 OUT_Z_MSB: Z_MSB Register (Read Only) (24)

0x06 OUT_Z_LSB: Z_LSB Register (Read Only) (24)

0x0B: SYSMOD System Mode Register (24)

0x0B SYSMOD: System Mode Register (Read Only) (24)

Table13. SYSMOD Description (24)

0x0C: INT_SOURCE System Interrupt Status Register (25)

Table14. INT_SOURCE Description (25)

0x0D: WHO_AM_I Device ID Register (26)

0x0D: WHO_AM_I Device ID Register (Read Only) (26)

0x0E: XYZ_DATA_CFG Register (26)

0x0E: XYZ_DATA_CFG (Read/Write) (26)

Table15. XYZ Data Configuration Descriptions (26)

Table16. Full Scale Range (26)

0x0F: HP_FILTER_CUTOFF High Pass Filter Register (26)

0x0F HP_FILTER_CUTOFF: High Pass Filter Register (Read/Write) (26)

Table17. High Pass Filter Cut-off Register Descriptions (26)

Table18. High Pass Filter Cut-off Options (27)

6.2Portrait/ Landscape Embedded Function Registers (27)

0x10: PL_STATUS Portrait/Landscape Status Register (27)

0x10 PL_STATUS Register (Read Only) (27)

Table19. PL_STATUS Register Description (27)

0x11 Portrait/Landscape Configuration Register (28)

0x11 PL_CFG Register (Read/Write (28)

Table20. PL_CFG Description (28)

0x12 Portrait/Landscape Debounce Counter (28)

0x12 PL_COUNT Register (Read/Write) (28)

Table21. PL_COUNT Description (28)

Table22. PL_COUNT Relationship with the ODR (28)

0x13: PL_BF_ZCOMP Back/Front and Z Compensation Register (28)

0x13: PL_BF_ZCOMP Register (Read/Write) (28)

Table23. PL_BF_ZCOMP Description (28)

0x14: P_L_THS_REG Portrait/Landscape Threshold and Hysteresis Register (29)

0x14: P_L_THS_REG Register (Read/Write) (29)

Table24. P_L_THS_REG Description (29)

Table25. Trip Angles with Hysteresis for 45° Angle (29)

6.3Motion and Freefall Embedded Function Registers (29)

Mode 1: Freefall Detection with ELE = 0, OAE = 0 (29)

Mode 2: Freefall Detection with ELE = 1, OAE = 0 (29)

Mode 3: Motion Detection with ELE = 0, OAE = 1 (29)

Mode 4: Motion Detection with ELE = 1, OAE = 1 (29)

0x15 FF_MT_CFG Freefall/Motion Configuration Register (30)

0x15 FF_MT_CFG Register (Read/Write) (30)

Table26. FF_MT_CFG Description (30)

Figure13. FF_MT_CFG High and Low g Level (30)

0x16 FF_MT_SRC Freefall/Motion Source Register (30)

0x16: FF_MT_SRC Freefall and Motion Source Register (Read Only) (30)

Table27. Freefall/Motion Source Description (31)

0x17: FF_MT_THS Freefall and Motion Threshold Register (31)

0x17 FF_MT_THS Register (Read/Write) (31)

Table28. FF_MT_THS Description (31)

MMA8452Q Sensors

Table30. FF_MT_COUNT Relationship with the ODR (32)

Figure14. DBCNTM Bit Function (33)

6.4Transient (HPF) Acceleration Detection (34)

0x1D: Transient_CFG Register (34)

0x1D TRANSIENT_CFG Register (Read/Write) (34)

Table31. TRANSIENT_CFG Description (34)

0x1E TRANSIENT_SRC Register (34)

0x1E TRANSIENT_SRC Register (Read Only) (34)

Table32. TRANSIENT_SRC Description (34)

0x1F TRANSIENT_THS Register (35)

0x1F TRANSIENT_THS Register (Read/Write) (35)

Table33. TRANSIENT_THS Description (35)

0x20 TRANSIENT_COUNT (35)

0x20 TRANSIENT_COUNT Register (Read/Write) (35)

Table34. TRANSIENT_COUNT Description (35)

Table35. TRANSIENT_COUNT Relationship with the ODR (35)

6.5Single, Double and Directional Tap Detection Registers (36)

0x21: PULSE_CFG Pulse Configuration Register (36)

0x21 PULSE_CFG Register (Read/Write) (36)

Table36. PULSE_CFG Description (36)

0x22: PULSE_SRC Pulse Source Register (36)

0x22 PULSE_SRC Register (Read Only) (36)

Table37. PULSE_SRC Description (36)

0x23 - 0x25: PULSE_THSX, Y, Z Pulse Threshold for X, Y & Z Registers (37)

0x23 PULSE_THSX Register (Read/Write) (37)

Table38. PULSE_THSX Description (37)

0x24 PULSE_THSY Register (Read/Write) (37)

Table39. PULSE_THSY Description (37)

0x25 PULSE_THSZ Register (Read/Write) (37)

Table40. PULSE_THSZ Description (37)

0x26: PULSE_TMLT Pulse Time Window 1 Register (37)

0x26 PULSE_TMLT Register (Read/Write) (37)

Table41. PULSE_TMLT Description (37)

Table42. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 1 (37)

Table43. Time Step for PULSE Time Limit (Reg 0x0F) Pulse_LPF_EN = 0 (38)

0x27: PULSE_LTCY Pulse Latency Timer Register (38)

0x27 PULSE_LTCY Register (Read/Write) (38)

Table44. PULSE_LTCY Description (38)

Table45. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 (38)

Table46. Time Step for PULSE Latency @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0 (38)

0x28 PULSE_WIND Register (Read/Write) (39)

Table47. PULSE_WIND Description (39)

Table48. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 1 (39)

Table49. Time Step for PULSE Detection Window @ ODR and Power Mode (Reg 0x0F) Pulse_LPF_EN = 0 (39)

6.6Auto-WAKE/SLEEP Detection (40)

0x29 ASLP_COUNT Register (Read/Write) (40)

Table50. ASLP_COUNT Description (40)

Table51. ASLP_COUNT Relationship with ODR (40)

Table52. SLEEP/WAKE Mode Gates and Triggers (40)

6.7Control Registers (41)

0x2A: CTRL_REG1 System Control 1 Register (41)

0x2A CTRL_REG1 Register (Read/Write) (41)

Table53. CTRL_REG1 Description (41)

Table54. SLEEP Mode Rate Description (41)

Table55. System Output Data Rate Selection (41)

Table56. Full Scale Selection (41)

MMA8452Q

Sensors

Table58. MODS Oversampling Modes (42)

Table59. MODS Oversampling Modes Current Consumption and Averaging Values at each ODR (42)

0x2C: CTRL_REG3 Interrupt Control Register (43)

0x2C CTRL_REG3 Register (Read/Write) (43)

Table60. CTRL_REG3 Description (43)

0x2D: CTRL_REG4 Register (Read/Write) (43)

0x2D CTRL_REG4 Register (Read/Write) (43)

Table61. Interrupt Enable Register Description (43)

0x2E CTRL_REG5 Register (Read/Write) (44)

0x2E: CTRL_REG5 Interrupt Configuration Register (44)

Table62. Interrupt Configuration Register Description (44)

6.8User Offset Correction Registers (44)

0x2F: OFF_X Offset Correction X Register (44)

0x2F OFF_X Register (Read/Write) (44)

Table63. OFF_X Description (44)

0x30: OFF_Y Offset Correction Y Register (44)

0x30 OFF_Y Register (Read/Write) (44)

Table64. OFF_Y Description (44)

0x31: OFF_Z Offset Correction Z Register (44)

0x31 OFF_Z Register (Read/Write) (44)

Table65. OFF_Z Description (44)

Table66. MMA8452Q Register Map (45)

Table67. Accelerometer Output Data (46)

Package Dimensions (47)

MMA8452Q Sensors

Sensors

MMA8452Q Application Notes for Reference

The following is a list of Freescale Application Notes written for the MMA8451, 2, 3Q: ?AN4068, Embedded Orientation Detection Using the MMA8451, 2, 3Q ?AN4069, Offset Calibration of the MMA8451, 2, 3Q

?AN4070, Motion and Freefall Detection Using the MMA8451, 2, 3Q ?AN4071, High Pass Data and Functions Using the MMA8451, 2,3Q ?AN4072, MMA8451, 2, 3Q Single/Double and Directional Tap Detection ?AN4073, Using the 32 Sample First In First Out (FIFO) in the MMA8451Q ?AN4074, Auto-Wake/Sleep Using the MMA8451, 2, 3Q

?AN4075, How Many Bits are Enough? The Trade-off Between High Resolution and Low Power Using Oversampling Modes ?AN4076, Data Manipulation and Basic Settings of the MMA8451, 2, 3Q

?AN4077, MMA8451, 2, 3Q Design Checklist and Board Mounting Guidelines

Block Diagram and Pin Description

1.1

Block Diagram

Figure 1. Block Diagram

1.2Pin Description

Figure 2. Direction of the Detectable Accelerations

SDA SCL

Auto-WAKE/SLEEP

ACTIVE Mode

SLEEP

MODE Options Low Power

Low Noise + Power High Resolution Normal

MODE Options Low Power

Low Noise + Power High Resolution Normal

ACTIVE Mode

WAKE

Sensors

MMA8452Q

Figure 3 shows the device configuration in the 6 different orientation modes. These orientations are defined as the following: PU = Portrait Up, LR = Landscape Right, PD = Portrait Down, LL = Landscape Left, BACK and FRONT side views. There are several registers to configure the orientation detection and are described in detail in the register setting section.

Figure 3. Landscape/Portrait Orientation

Top View

Earth Gravity

Pin 1

Xout @ 0g Yout @ -1g Zout @ 0g

Xout @ 1g Yout @ 0g Zout @ 0g

Xout @ 0g Yout @ 1g Zout @ 0g

Xout @ -1g Yout @ 0g Zout @ 0g

Side View

FRONT

Xout @ 0g Yout @ 0g Zout @ 1g

BACK

Xout @ 0g Yout @ 0g Zout @ -1g

Table1. Pin Description

Pin #Pin Name Description Pin Status

1VDDIO Internal Power Supply (1.62 V - 3.6 V)Input

2BYP Bypass capacitor (0.1 μF)Input

3NC Leave open. Do not connect.Open

4SCL I2C Serial Clock Open Drain

5GND Connect to Ground Input

6SDA I2C Serial Data Open Drain

7SA0I2C Least Significant Bit of the Device I2C Address Input

8NC Internally not connected (can be GND or VDD)Input

9INT2Inertial Interrupt 2Output

10GND Connect to Ground Input

11INT1Inertial Interrupt 1Output

12GND Connect to Ground Input

13NC Internally not connected (can be GND or VDD)Input

14VDD Power Supply (1.95 V - 3.6 V)Input

15NC Internally not connected (can be GND or VDD)Input

16NC Internally not connected (can be GND or VDD)Input The device power is supplied through VDD line. Power supply decoupling capacitors (100 nF ceramic plus 4.7 μF bulk, or a single 4.7 μF ceramic) should be placed as near as possible to the pins 1 and 14 of the device.

The control signals SCL, SDA, and SA0 are not tolerant of voltages more than VDDIO + 0.3 V. If VDDIO is removed, the control signals SCL, SDA, and SA0 will clamp any logic signals with their internal ESD protection diodes.

The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) are user programmable through the I2C interface. The SDA and SCL I2C connections are open drain and therefore require a pull-up resistor as shown in the application diagram in Figure 4.

1.3Soldering Information

The QFN package is compliant with the RoHS standard. Please refer to AN4077.

MMA8452Q

Sensors

MMA8452Q

Mechanical and Electrical Specifications

2.1

Mechanical Characteristics

Table 2. Mechanical Characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted .

Parameter

Test Conditions Symbol

Min

Typ Max

Unit

Measurement Range (1)

1.Dynamic Range is limited to 4g when the Low Noise bit in Register 0x2A, bit 2 is set.

FS[1:0] set to 00

2g Mode

±2

FS[1:0] set to 01

4g Mode ±4FS[1:0] set to 10

8g Mode ±8Sensitivity

FS[1:0] set to 00

2g Mode

1024

counts/g FS[1:0] set to 01

4g Mode 512FS[1:0] set to 10

8g Mode

256

Sensitivity Accuracy (2)

2.Sensitivity remains in spec as stated, but changing Oversampling mode to Low Power causes 3% sensitivity shift. This behavior is also seen when changing from 800 Hz to any other data rate in the Normal, Low Noise + Low Power or High Resolution mode.Soa

±2.5

%Sensitivity Change vs. Temperature

FS[1:0] set to 00

2g Mode

TCSo ±0.008%/°C

FS[1:0] set to 01

4g Mode FS[1:0] set to 10

8g Mode

Zero-g Level Offset Accuracy (3)

3.Before board mount.

FS[1:0] 2g, 4g, 8g TyOff ±20 mg Zero-g Level Offset Accuracy Post Board Mount (4)4.Post Board Mount Offset Specifications are based on an 8 Layer PCB, relative to 25°C.FS[1:0] 2g, 4g, 8g TyOffPBM ±30 mg Zero-g Level Change vs. Temperature -40°C to 85°C

TCOff

±0.15

mg/°C

Self-Test Output Change (5)X Y Z

5.Self-Test is one direction only.

FS[1:0] set to 0 4g Mode

Vst

+45+64+420

LSB

ODR Accuracy 2 MHz

±2

Output Data Bandwidth BW

ODR/3

ODR/2

Hz Output Noise

Normal Mode ODR = 400 Hz Noise 126 μg/√Hz Output Noise Low Noise Mode (1)Normal Mode ODR = 400 Hz

Noise 99

μg/√Hz

Operating Temperature Range

Top

-40

+85

°C

Sensors

MMA8452Q 2.2Electrical Characteristics

Table 3. Electrical Characteristics @ VDD = 2.5 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted .

Parameter

Test Conditions

Symbol Min Typ Max Unit Supply Voltage

VDD (1)1.There is no requirement for power supply sequencing. The VDDIO input voltage can be higher than the VDD input voltage.

1.95

2.5

3.6 V Interface Supply Voltage

VDDIO (1)

1.62

1.8 3.6

Low Power Mode

ODR = 1.56 Hz I dd LP

6μA

ODR = 6.25 Hz 6ODR = 12.5 Hz

6ODR = 50 Hz 14ODR = 100 Hz 24ODR = 200 Hz 44ODR = 400 Hz 85ODR = 800 Hz 165Normal Mode

ODR = 1.56 Hz I dd 24μA ODR = 6.25 Hz 24ODR = 12.5 Hz

24ODR = 50 Hz 24ODR = 100 Hz 44ODR = 200 Hz 85ODR = 400 Hz 165ODR = 800 Hz

Current during Boot Sequence, 0.5 mSec max duration using recommended Bypass Cap VDD = 2.5 V Idd Boot 1μA Value of Capacitor on BYP pin -40°C 85°C

Cap 75

100470 nF STANDBY Mode Current @25°C VDD = 2.5 V, VDDIO = 1.8 V

STANDBY Mode

I dd Stby

1.8

μA Digital High Level Input Voltage SCL, SDA, SA0

VIH 0.75*VDDIO

V Digital Low Level Input Voltage SCL, SDA, SA0

VIL 0.3*VDDIO

V High Level Output Voltage INT1, INT2

I O = 500 μA VOH 0.9*VDDIO

V Low Level Output Voltage INT1, INT2

I O = 500 μA VOL 0.1*VDDIO V Low Level Output Voltage SDA

I O = 500 μA VOLS

0.1*VDDIO

V Power on Ramp Time

0.0011000 ms Time from VDDIO on and VDD > Vmin until I 2C ready for operation

Cbyp = 100 nF

BT —

350

500

μs Turn-on time (STANDBY to ACTIVE)Ton 2/ODR + 1 ms s Turn-on time (Power Down to ACTIVE Mode)Ton 2/ODR + 2 ms

s Operating Temperature Range

Top

-40

+85

°C

Sensors

MMA8452Q

2.3

I 2C Interface Characteristic

Table 4. I 2C Slave Timing Values (1)

1.All values referred to VIH (min) and VIL (max) levels.

Parameter

Symbol

I 2C Fast Mode Unit

Min Max SCL Clock Frequency

Pull-up = 4.7 k Ω, Cb = 20 pF Pull-up = 4.7 k Ω, Cb = 40 pF Pull-up = 4.7 k Ω, Cb = 400 pF Pull-up = 1 k Ω, Cb = 20 pF Pull-up = 1 k Ω, Cb = 400 pF

f SCL

00000 2.250100

Non-functional

4.50750

MHz kHz —MHz kHz Bus Free Time between STOP and START Condition t BUF 1.3μs Repeated START Hold Time t HD;STA 0.6μs Repeated START Set-up Time t SU;STA 0.6μs STOP Condition Set-up Time t SU;STO 0.6μs SDA Data Hold Time (2)2.t HD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

t HD;DAT 50

(3)

3.The maximum t HD;DAT could be 3.45 μs and 0.9 μs for Standard mode and Fast mode, but must be less than the maximum of t VD;DAT or t VD;ACK by a transition time.

μs SDA Valid Time (4)

4.t VD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

t VD;DAT 0.9(3)μs SDA Valid Acknowledge Time (5)5.t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

t VD;ACK 0.9(3)

μs SDA Set-up Time t SU;DAT 100(6)6.A Fast mode I 2C device can be used in a Standard mode I 2C system, but the requirement t SU;DAT 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r (max) + t SU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I 2C specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time ns SCL Clock Low Time t LOW 4.7μs SCL Clock High Time t HIGH 4

μs

SDA and SCL Rise Time t r 1000ns SDA and SCL Fall Time (7) (8)

7.Cb = total capacitance of one bus line in pF.

8.The maximum t f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f is specified at 250ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t f .

t f 300ns Pulse width of spikes on SDA and SCL that must be suppressed by input filter

t SP

Sensors

MMA8452Q Figure 5. I 2

C Slave Timing Diagram

2.4Absolute Maximum Ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. Exposure to maximum rating conditions for extended periods may affect device reliability.Table 5. Maximum Ratings

Rating

Symbol Value Unit Maximum Acceleration (all axes, 100 μs)g max 5,000g Supply Voltage

VDD -0.3 to + 3.6V Input voltage on any control pin (SA0, SCL, SDA)Vin -0.3 to VDDIO + 0.3

V Drop Test

D drop 1.8m Operating Temperature Range T OP -40 to +85°C Storage Temperature Range

T STG

-40 to +125

°C

Table

6. ESD and Latch-Up Protection Characteristics

Rating

Symbol Value Unit Human Body Model HBM ±2000V Machine Model MM ±200V Charge Device Model CDM ±500V Latch-up Current at T = 85°C

—

±100

This device is sensitive to mechanical shock. Improper handling can cause permanent damage of the part or cause the part to otherwise fail.

This is an ESD sensitive, improper handling can cause permanent damage to the part.

Sensors

MMA8452Q

Terminology

3.1

Sensitivity

The sensitivity is represented in counts/g. In 2g mode the sensitivity is 1024 counts/g. In 4g mode the sensitivity is 512 counts/g and in 8g mode the sensitivity is 256 counts/g.

3.2Zero-g Offset

Zero-g Offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if the sensor is stationary. A sensor stationary on a horizontal surface will measure 0g in X-axis and 0g in Y -axis whereas the Z-axis will measure 1g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT Registers 0x00, data expressed as 2's complement number). A deviation from ideal value in this case is called Zero-g offset. Offset is to some extent a result of stress on the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress.

3.3Self-Test

Self-T est checks the transducer functionality without external mechanical stimulus. When Self-T est is activated, an electrostatic actuation force is applied to the sensor, simulating a small acceleration. In this case the sensor outputs will exhibit a change in their DC levels which are related to the selected full scale through the device sensitivity . When Self-T est is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force.

4Modes of Operation

Figure 6. MMA8452Q Mode Transition Diagram

All register contents are preserved when transitioning from ACTIVE to STANDBY mode. Some registers are reset when transitioning from STANDBY to ACTIVE. These are all noted in the device memory map register table. The SLEEP and WAKE modes are ACTIVE modes. For more information on how to use the SLEEP and WAKE modes and how to transition between these modes please refer to the functionality section of this document.

Table 7. Mode of Operation Description

Mode I 2C Bus State VDD VDDIO

Function Description

OFF

Powered Down

<1.8 V

VDDIO Can be > VDD The device is powered off. All analog and digital blocks are shutdown. I 2C bus inhibited.

STANDBY

I 2C communication with MMA8452Q is possible ON

VDDIO = High VDD = High

ACTIVE bit is cleared Only digital blocks are enabled.

Analog subsystem is disabled. Internal clocks disabled.

ACTIVE (WAKE/SLEEP)

I 2C communication with MMA8452Q is possible

ON VDDIO = High VDD = High

ACTIVE bit is set

All blocks are enabled (digital, analog).

SLEEP

WAKE

STANDBY

OFF

ACTIVE

5Functionality

The MMA8452Q is a low-power, digital output 3-axis linear accelerometer with a I2C interface and embedded logic used to detect events and notify an external microprocessor over interrupt lines. The functionality includes the following:?8-bit or 12-bit data which includes High Pass Filtered data

? 4 different oversampling options for compromising between resolution and current consumption based on application requirements

?Additional Low Noise mode that functions independently of the Oversampling modes for higher resolution

?Low Power and Auto-WAKE/SLEEP for conservation of current consumption

?Single/Double tap with directional information 1 channel

?Motion detection with directional information or Freefall 1 channel

?Transient/Jolt detection based on a high pass filter and settable threshold for detecting the change in acceleration above

a threshold with directional information 1 channel

?Portrait/Landscape detection with trip points fixed at 30° and 60° for smooth transitions between orientations.

All functionality is available in 2g, 4g or 8g dynamic ranges. There are many configuration settings for enabling all the different functions. Separate application notes have been provided to help configure the device for each embedded functionality.

5.1Device Calibration

The device interface is factory calibrated for sensitivity and Zero-g offset for each axis. The trim values are stored in Non Volatile Memory (NVM). On power-up, the trim parameters are read from NVM and applied to the circuitry. In normal use, further calibration in the end application is not necessary. However, the MMA8452Q allows the user to adjust the Zero-g offset for each axis after power-up, changing the default offset values. The user offset adjustments are stored in 6 volatile registers. For more information on device calibration, refer to Freescale application note, AN4069.

5.28-bit or 12-bit Data

The measured acceleration data is stored in the OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB registers as 2’s complement 12-bit numbers. The most significant 8-bits of each axis are stored in OUT_X (Y,

Z)_MSB,so applications needing only 8-bit results can use these 3 registers and ignore OUT_X,Y, Z_LSB. To do this, the

F_READ bit in CTRL_REG1 must be set. When the F_READ bit is cleared, the fast read mode is disabled.

When the full-scale is set to 2g, the measurement range is -2g to +1.999g, and each count corresponds to 1g/1024

(1 mg) at 12-bits resolution. When the full-scale is set to 8g, the measurement range is -8g to +7.996g, and each count corresponds to 1g/256 (3.9 mg) at 12-bits resolution. The resolution is reduced by a factor of 16 if only the 8-bit results are used. For more information on the data manipulation between data formats and modes, refer to Freescale application note, AN4076. There is a device driver available that can be used with the Sensor T oolbox demo board (LFSTBEB8451, 2, 3Q) with this application note.

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5.3Low Power Modes vs. High Resolution Modes

The MMA8452Q can be optimized for lower power modes or for higher resolution of the output data. High resolution is achieved by setting the LNOISE bit in Register 0x2A. This improves the resolution but be aware that the dynamic range is limited to 4g when this bit is set. This will affect all internal functions and reduce noise. Another method for improving the resolution of the data is by oversampling. One of the oversampling schemes of the data can activated when MODS = 10 in Register 0x2B which will improve the resolution of the output data only. The highest resolution is achieved at 1.56 Hz.

There is a trade-off between low power and high resolution. Low Power can be achieved when the oversampling rate is reduced. When MODS = 11 the lowest power is achieved. The lowest power is achieved when the sample rate is set to 1.56 Hz. For more information on how to configure the MMA8452Q in Low Power mode or High Resolution mode and to realize the benefits, refer to Freescale application note, AN4075.

5.4Auto-WAKE/SLEEP Mode

The MMA8452Q can be configured to transition between sample rates (with their respective current consumption) based on four of the interrupt functions of the device. The advantage of using the Auto-WAKE/SLEEP is that the system can automatically transition to a higher sample rate (higher current consumption) when needed but spends the majority of the time in the SLEEP mode (lower current) when the device does not require higher sampling rates. Auto-WAKE refers to the device being triggered by one of the interrupt functions to transition to a higher sample rate. This may also interrupt the processor to transition from a SLEEP mode to a higher power mode.

SLEEP mode occurs after the accelerometer has not detected an interrupt for longer than the user definable time-out period. The device will transition to the specified lower sample rate. It may also alert the processor to go into a lower power mode to save on current during this period of inactivity.

The Interrupts that can WAKE the device from SLEEP are the following: T ap Detection, Orientation Detection, Motion/Freefall, and Transient Detection. Refer to AN4074, for more detailed information for configuring the Auto-WAKE/SLEEP.

5.5Freefall and Motion Detection

MMA8452Q has flexible interrupt architecture for detecting either a Freefall or a Motion. Freefall can be enabled where the set threshold must be less than the configured threshold, or motion can be enabled where the set threshold must be greater than the threshold. The motion configuration has the option of enabling or disabling a high pass filter to eliminate tilt data (static offset). The freefall does not use the high pass filter. For details on the Freefall and Motion detection with specific application examples and recommended configuration settings, refer to Freescale application note AN4070.

5.5.1Freefall Detection

The detection of “Freefall” involves the monitoring of the X, Y, and Z axes for the condition where the acceleration magnitude is below a user specified threshold for a user definable amount of time. Normally the usable threshold ranges are between

±100 mg and ±500 mg.

5.5.2Motion Detection

Motion is often used to simply alert the main processor that the device is currently in use. When the acceleration exceeds a set threshold the motion interrupt is asserted. A motion can be a fast moving shake or a slow moving tilt. This will depend on the threshold and timing values configured for the event. The motion detection function can analyze static acceleration changes or faster jolts. For example, to detect that an object is spinning, all three axes would be enabled with a threshold detection of > 2g. This condition would need to occur for a minimum of 100 ms to ensure that the event wasn't just noise. The timing value is set by a configurable debounce counter. The debounce counter acts like a filter to determine whether the condition exists for configurable set of time (i.e., 100 ms or longer). There is also directional data available in the source register to detect the direction of the motion. This is useful for applications such as directional shake or flick, which assists with the algorithm for various gesture detections.

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MMA8452Q 5.6Transient Detection

The MMA8452Q has a built-in high pass filter. Acceleration data goes through the high pass filter, eliminating the offset (DC) and low frequencies. The high pass filter cut-off frequency can be set by the user to four different frequencies which are

dependent on the Output Data Rate (ODR). A higher cut-off frequency ensures the DC data or slower moving data will be filtered out, allowing only the higher frequencies to pass. The embedded Transient Detection function uses the high pass filtered data allowing the user to set the threshold and debounce counter. The Transient detection feature can be used in the same manner as the motion detection by bypassing the high pass filter. There is an option in the configuration register to do this. This adds more flexibility to cover various customer use cases.

Many applications use the accelerometer’s static acceleration readings (i.e., tilt) which measure the change in acceleration due to gravity only . These functions benefit from acceleration data being filtered with a low pass filter where high frequency data is considered noise. However, there are many functions where the accelerometer must analyze dynamic acceleration. Functions such as tap, flick, shake and step counting are based on the analysis of the change in the acceleration. It is simpler to interpret these functions dependent on dynamic acceleration data when the static component has been removed. The Transient Detection function can be routed to either interrupt pin through bit 5 in CTRL_REG5 register (0x2E). Registers 0x1D – 0x20 are the

dedicated Transient Detection configuration registers. The source register contains directional data to determine the direction of the acceleration, either positive or negative. For details on the benefits of the embedded Transient Detection function along with specific application examples and recommended configuration settings, please refer to Freescale application note, AN4071.

5.7Tap Detection

The MMA8452Q has embedded single/double and directional tap detection. This function has various customizing timers for setting the pulse time width and the latency time between pulses. There are programmable thresholds for all three axes. The tap detection can be configured to run through the high pass filter and also through a low pass filter, which provides more customizing and tunable tap detection schemes. The status register provides updates on the axes where the event was detected and the direction of the tap. For more information on how to configure the device for tap detection please refer to Freescale application note AN4072.

5.8Orientation Detection

The MMA8452Q has an orientation detection algorithm with the ability to detect all 6 orientations. The transition from portrait to landscape is fixed with a 45° threshold angle and a ±14° hysteresis angle. This allows the for a smooth transition from portrait to landscape at approximately 30° and then from landscape to portrait at approximately 60°.

The angle at which the device no longer detects the orientation change is referred to as the “Z-Lockout angle”. The device operates down to 29° from the flat position. All angles are accurate to ±2°.

For further information on the orientation detection function refer to Freescale application note, AN4068.

Figure 8 and Figure 9 show the definitions of the trip angles going from Landscape to Portrait and then also from Portrait to Landscape.

Figure

7. Landscape/Portrait Orientation

Top View

Earth Gravity

Pin 1

Yout @ -1g Zout @ 0g

Xout @ 1g Yout @ 0g Zout @ 0g

Yout @ 1g Zout @ 0g

Xout @ -1g Yout @ 0g Zout @ 0g

Side View

FRONT

Xout @ 0g Yout @ 0g

Zout @ 1g

BACK

Xout @ 0g Yout @ 0g Zout @ -1g

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MMA8452Q

Figure 8. Illustration of Landscape to Portrait Transition Figure 9. Illustration of Portrait to Landscape Transition

Figure 10 illustrates the Z-angle lockout region. When lifting the device upright from the flat position it will be active for orientation detection as low as 29° from flat. .

Figure 10. Illustration of Z-Tilt Angle Lockout Transition

PORTRAIT Landscape to Portrait 90°Trip Angle = 60°

0° Landscape PORTRAIT 90°

0° Landscape

UPRIGHT 90°

0° FLAT

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MMA8452Q 5.9Interrupt Register Configurations

There are six configurable interrupts in the MMA8452Q: Data Ready , Motion/Freefall, T ap (Pulse), Orientation, Transient, and Auto-SLEEP events. These six interrupt sources can be routed to one of two interrupt pins. The interrupt source must be enabled and configured. If the event flag is asserted because the event condition is detected, the corresponding interrupt pin, INT1 or INT2, will assert.

Figure 11. System Interrupt Generation Block Diagram

5.10

Serial I 2C Interface

Acceleration data may be accessed through an I 2C interface thus making the device particularly suitable for direct interfacing with a microcontroller. The MMA8452Q features an interrupt signal which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in the digital system that uses the device. The MMA8452Q may also be configured to generate other interrupt signals accordingly to the programmable embedded functions of the device for Motion, Freefall, Transient, Orientation, and T ap.The registers embedded inside the MMA8452Q are accessed through the I 2C serial interface (Table 8). To enable the I 2C interface, VDDIO line must be tied high (i.e., to the interface supply voltage). If VDD is not present and VDDIO is present, the MMA8452Q is in off mode and communications on the I 2C interface are ignored. The I 2C interface may be used for communications between other I 2C devices and the MMA8452Q does not affect the I 2C bus.

There are two signals associated with the I 2C bus; the Serial Clock Line (SCL) and the Serial Data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. External pull-up resistors connected to VDDIO are expected for SDA and SCL. When the bus is free both the lines are high. The I 2C interface is compliant with fast mode (400 kHz), and Normal mode (100 kHz) I 2C standards (Table 4).

Table 8. Serial Interface Pin Description

Pin Name Pin Description

SCL I 2C Serial Clock SDA I 2C Serial Data

SA0

I 2C least significant bit of the device address

INTERRUPT CONTROLLER

Data Ready Motion/Freefall Tap (Pulse)Orientation

Transient Auto-SLEEP

INT ENABLE

INT CFG

INT1

INT2

5.10.1I2C Operation

The transaction on the bus is started through a start condition (ST ART) signal. ST ART condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After ST ART has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after ST ART contains the slave address in the first 7 bits, and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The 9th clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock period.

A LOW to HIGH transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer is always terminated by a STOP. A Master may also issue a repeated ST ART during a data transfer. The MMA8452Q expects repeated ST ART s to be used to randomly read from specific registers.

The MMA8452Q's standard slave address is a choice between the two sequential addresses 0011100 and 0011101. The selection is made by the high and low logic level of the SA0 (pin 7) input respectively. The slave addresses are factory programmed and alternate addresses are available at customer request. The format is shown in Table9.

Table9. I2C Address Selection Table

Slave Address (SA0 = 0)Slave Address (SA0 = 1)Comment 0011100 (0x1C)0011101 (0x1D)Factory Default

Single Byte Read

The MMA8452Q has an internal ADC that can sample, convert and return sensor data on request. The transmission of an 8-bit command begins on the falling edge of SCL. After the eight clock cycles are used to send the command, note that the data returned is sent with the MSB first once the data is received. Figure 12shows the timing diagram for the accelerometer 8-bit I2C read operation. The Master (or MCU) transmits a start condition (ST) to the MMA8452Q, slave address ($1D), with the R/W bit set to “0” for a write, and the MMA8452Q sends an acknowledgement. Then the Master (or MCU) transmits the address of the register to read and the MMA8452Q sends an acknowledgement. The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8452Q ($1D) with the R/W bit set to “1” for a read from the previously selected register. The Slave then acknowledges and transmits the data from the requested register. The Master does not acknowledge (NAK) the transmitted data, but transmits a stop condition to end the data transfer.

Multiple Byte Read

When performing a multi-byte read or “burst read”, the MMA8452Q automatically increments the received register address commands after a read command is received. Therefore, after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each MMA8452Q acknowledgment (AK) is received until a no acknowledge (NAK) occurs from the Master followed by a stop condition (SP) signaling an end of transmission.

Single Byte Write

T o start a write command, the Master transmits a start condition (ST) to the MMA8452Q, slave address ($1D) with the R/W bit set to “0” for a write, the MMA8452Q sends an acknowledgement. Then the Master (MCU) transmits the address of the register to write to, and the MMA8452Q sends an acknowledgement. Then the Master (or MCU) transmits the 8-bit data to write to the designated register and the MMA8452Q sends an acknowledgement that it has received the data. Since this transmission is complete, the Master transmits a stop condition (SP) to the data transfer. The data sent to the MMA8452Q is now stored in the appropriate register.

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MMA8452Q Multiple Byte Write

The MMA8452Q automatically increments the received register address commands after a write command is received.

Therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MMA8452Q acknowledgment (ACK) is received.

Figure 12. I 2C Timing Diagram

Table 10. I 2C Device Address Sequence

Command [6:1]

Device Address

[0]SA0[6:0]

Device Address

R/W 8-bit Final Value

Read 00111000x1C 10x39Write 00111000x1C 00x38Read 00111010x1D 10x3B Write

001110

0x1D

0x3A

< Single Byte Read >Master

Device Address[6:0]

NAK SP

Slave AK AK AK Data[7:0]

< Multiple Byte Read >Master

Device Address[6:0]

SR Device Address[6:0]

Slave

AK AK AK Data[7:0]

Master

AK AK NAK SP

Slave Data[7:0]Data[7:0]Data[7:0]

< Single Byte Write >Master

Device Address[6:0]

Data[7:0]

Slave AK AK AK

< Multiple Byte Write >Master

Device Address[6:0]

Data[7:0]

Slave

AK AK AK AK

Legend

ST: Start Condition

SP: Stop Condition NAK: No Acknowledge W: Write = 0

SR: Repeated Start Condition

AK: Acknowledge

R: Read = 1