W27C257-10中文资料
32K × 8 ELECTRICALLY ERASABLE EPROM
Publication Release Date: September 1998
GENERAL DESCRIPTION
The W27C257 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 32768 × 8 bits that operates on a single 5 volt power supply. The W27C257provides an electrical chip erase function. This part was the same EPROM Writer's utilities as the W27E257.
FEATURES
?High speed access time:100/120 nS (max.)
?Read operating current: 30 mA (max.)?Erase/Programming operating current 30 mA (max.)
?Standby current: 1 mA (max.)?
Single 5V power supply
?+14V erase/+12V programming voltage ?Fully static operation
?All inputs and outputs directly TTL/CMOS
compatible
?Three-state outputs
?Available packages: 28-pin 600 mil DIP and 32-pin PLCC
PIN CONFIGURATIONS
BLOCK DIAGRAM
PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C257 has two control functions, both of which produce data at the outputs.
CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (T ACC) is equal to the delay from CE to output (T CE), and data are available at the outputs T OE after the falling edge of OE, if T ACC and T CE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C257 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.
Erase mode is entered when V PP is raised to V PE (14V), V CC = V CE (5V), OE = V IH (2V or above but lower than V CC), A9 = V HH (14V), A0 = V IL (0.8V or below but higher than GND), and all other address pins equal V IL and data input pins equal V IH. Pulsing CE low starts the erase operation. Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if V PP = V PE (14V), CE = V IH, and OE = V IL.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when V PP is raised to V PP (12V), V CC = V CP (5V), OE = V IH, the address pins equal the desired address, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether or not they have been successfully programmed with the desired data. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if V PP = V PP (12V), CE = V IH, IL.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE = V IH, erasing or programming of non-target chips is inhibited, so that except for the CE and OE pins, the W27C257 may have common inputs.
Publication Release Date: September 1998
Standby Mode
The standby mode significantly reduces V CC current. This mode is entered when CE = V IH . In standby mode, all outputs are in a high impedance state, independent of OE.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27C257 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (I SB ), active current levels (I CC ), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 μF ceramic capacitor connected between its V CC and GND. This high frequency, low inherent-inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 μF electrolytic capacitor should be placed at the array's power supply connection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
(V PP = 12V, V PE = 14V, V HH = 12V, V CP = 5V, X = V IH or V IL )
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT Ambient Temperature with Power Applied-55 to +125°C Storage Temperature-65 to +125°C Voltage on all pins with Respect to Ground Except V PP, A9
-0.5 to V CC +0.5V and V CC pins
Voltage on V PP Pin with Respect to Ground-0.5 to +14.5V Voltage on A9 Pin with Respect to Ground-0.5 to +14.5V Voltage on V CC Pin with Respect to Ground-0.5 to +7V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC Erase Characteristics
A CC
Note: V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP.
CAPACITANCE
(V CC = 5V, T A = 25° C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MAX.UNIT Input Capacitance C IN V IN = 0V6pF Output Capacitance C OUT V OUT = 0V12pF
Publication Release Date: September 1998
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels 0.45V to 2.4V Input Rise and Fall Times
10 nS Input and Output Timing Reference Level 0.8V/2.0V
Output Load
C L = 100 pF, I OH /I OL = -0.4 mA/2.1 mA
AC Test Load and Waveform
READ OPERATION DC CHARACTERISTICS
(V CC = 5.0V ±5%, T A = 0 to 70° C)
READ OPERATION AC CHARACTERISTICS
(V CC = 5.0V ±5%, T A = 0 to 70° C)
Note: V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP .
Publication Release Date: September 1998
DC PROGRAMMING CHARACTERISTICS
(V CC = 5.0V ±5%, T A = 25° C ±5° C)
AC PROGRAMMING/ERASE CHARACTERISTICS
(V CC = 5.0V ±5%, T A = 25° C ±5°
C)
Note: V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP .
TIMING WAVEFORMS
AC Read Waveform
Erase Waveform
Publication Release Date: September 1998
Timing Waveforms, continued
Programming Waveform
SMART PROGRAMMING ALGORITHM
Publication Release Date: September 1998
SMART ERASE ALGORITHM
ORDERING INFORMATION
PART NO.
ACCESS TIME (nS)
POWER SUPPLY CURRENT MAX.
(mA)
STANDBY V CC CURRENT MAX.
(μA)
PACKAGE
W27C257-1010030100600 mil DIP W27C257-1212030100600 mil DIP W27C257P-101003010032-pin PLCC W27C257P-12
120
30
100
32-pin PLCC
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
Publication Release Date: September 1998
PACKAGE DIMENSIONS
28-pin P-DIP
32-pin PLCC
VERSION HISTORY
VERSION
DATE PAGE
DESCRIPTION
A1Mar. 1998
Initial Issued
A2
Sep. 1998
6Correct Imput High Voltage (V IH ) from 2.0 (min) to 2.2 (max)4 , 6, 7Correct Vcc from 5.0 ±10% to 5.0 ±5%
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Rm. 803, World Trade Square, Tower II,123 Hoi Bun Rd., Kwun Tong,Kowloon, Hong Kong TEL: 852-********FAX: 852-********Winbond Electronics North America Corp.Winbond Memory Lab.
Winbond Microelectronics Corp.Winbond Systems Lab.
2727 N. First Street, San Jose,CA 95134, U.S.A.TEL: 408-9436666FAX: 408-5441798
Note: All data and specifications are subject to change without notice.