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verilog冒泡排序算法

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:24:00 04/25/2013
// Design Name:
// Module Name: maopaopaixu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module maopaopaixu(
input clk,
input rst,
input Send,
input Sort,
input Load,
input[7:0] Data_in,

output Waiting,
output Busy,
output Ready,
output reg[7:0] Data_out

);

assign Waiting = current_state == S_wait;
assign Busy = current_state == S_sort;
assign Ready = current_state == S_idle;
//assign Data_out = Send ? A[8] : 8'd0;
always @(posedge clk) begin
if(rst)
Data_out <= 8'd0;
else if(!done & current_state==S_send)
Data_out <= A[8];
else
Data_out <= 8'd0;
end


parameter S_rst = 3'd0;
parameter S_init = 3'd1;
parameter S_idle = 3'd2;
parameter S_load = 3'd3;
parameter S_prep = 3'd4;
parameter S_sort = 3'd5;
parameter S_wait = 3'd6;
parameter S_send = 3'd7;


reg[2:0] next_state;
reg[2:0] current_state;

reg[3:0] k;
reg[3:0] j;
reg[3:0] i;
parameter N = 8;

reg gt;
reg i_lte_N;
reg j_gte_i;
reg done;


reg[8:1] A[8:1];
//reg ld;
//reg set_i;
//reg incr_i;
//reg set_j;
//reg clr_k;
//reg incr_k;
//reg swap;
//reg send;

//always @(posedge clk) begin
always @(*) begin
// if(rst)
// gt <= 1'd0;
// else if(A[j-1]>A[j])
if(A[j-1]>A[j])
gt = 1'd1;
else
gt = 1'd0;
end


//always @(posedge clk) begin
always @(*) begin
// if(rst)
// i_lte_N <= 1'd0;
// else if(i<=N)
if(i<=N)
i_lte_N = 1'd1;
else
i_lte_N = 1'd0;
end

//always @(posedge clk) begin
always @(*) begin
// if(rst)
// j_gte_i <= 1'd0;
// else if(i<=j)
if(i<=j)
j_gte_i = 1'd1;
else
j_gte_i = 1'd0;
end

always @(*) begin
// if(rst)
// done <= 1'd0;
// else if(k==N-1)
if(k==N)
done = 1'd1;
else
done = 1'd0;
end

always @(posedge clk) begin
if(rst)
current_state <= S_rst;
else
current_state <= next_state;
end

always @(*) begin
case(current_state)
S_rst: next_state = S_init;

S_init: next_state = S_idle;

S_idle: begin
if(Load)
next_state = S_load;
else if(Sort)
next_state = S_prep;
else
next_state = S_idle;
end

S_load: begin
if(done)
next_state = S_init;
else
next_state = S_load;
end

S_prep: begin
//if(gt)
next_state = S_sort;
//else

end

S_sort: begin
if(j_gte_i)
next_state = S_sort;
else if(i_lte_N)
next_state = S_sort;
else if(Send)
next_state = S_send;
else
next_state = S_wait;

end

S_wait: begin
if(Send)
next_state = S_send;
else
next_state = S_wait;
end

S_send: begin
if(done)
next_state = S_init;
else
next_state = S_send;
end
endcase

end

always @(posedge clk) begin
if(rst)
k <= 4'd0;
else if(current_state==S_init)
k <= 4'd0;
else if(!done & current_state==S_load)
k <= k + 4'b1;
else if(!j_gte_i & !i_lte_N & Send & current_state==S_sort)
k <= 4'd0;
else if(!done & current_state==S_send)
k <= k + 4'd1;
end

always @(posedge clk) begin
if(rst) begin
A[1] <= 8'd0;
A[2] <= 8'd0;
A[3] <= 8'd0;
A[4] <= 8'd0;
A[5] <= 8'd0;
A[6] <= 8'd0;
A[7] <= 8'd0;
A[8] <= 8'd0;
end
else if(!done & current_state==S_load)
begin
A[1] <= Data_in;
A[2] <= A[1];
A[3] <= A[2];
A[4] <= A[3];
A[5] <= A[4];
A[6] <= A[5];
A[7] <= A[6];
A[8] <= A[7];
end
else if(!gt & current_state==S_prep)
begin
A[j] <= A[j-1];
A[j-1] <= A[j];
end
else if(j_gte_i & gt & current_state==S_sort)
begin
A[j] <= A[j-1];
A[j-1] <= A[j];
end
else if(!done & current_state==S_send)
begin
A[1] <= 8'd0;
A[2] <= A[1];
A[3] <= A[2];
A[4] <= A[3];
A[5] <= A[4];
A[6] <= A[5];
A[7] <= A[6];
A[8] <= A[7];
end
end


always @(posedge clk) begin
if(rst)
begin
i <= 4'd0;
end
else if(!Load & Sort & current_state==S_idle)
i <= 4'd2;
else if(!j_gte_i & i_lte_N & current_state==S_sort)
i <= i + 4'd1;
end

always @(posedge clk) begin
if(rst)
begin
j <= 4'd0;
end
else if(!Load & Sort & current_state==S_idle)
j <= N;
else if(!gt & current_state==S_prep)
j <= j-4'd1;
else if(current_state==S_sort & j_gte_i)
j <= j-4'd1;
else if(current_state==S_sort &!j_gte_i & i_lte_N)
j <= N;

end



endmodule

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