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GS8321E18GE-225中文资料

GS8321E18/32/36E-250/225/200/166/150/133

2M x 18, 1M x 32, 1M x 3636Mb Sync Burst SRAMs

250 MHz –133 MHz 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O

165-Bump FP-BGA Commercial Temp Industrial Temp Features

? FT pin for user-configurable flow through or pipeline operation

? Dual Cycle Deselect (DCD) operation

? IEEE 1149.1 JTAG-compatible Boundary Scan ? 2.5 V or 3.3 V +10%/–10% core power supply ? 2.5 V or 3.3 V I/O supply

? LBO pin for Linear or Interleaved Burst mode

? Internal input resistors on mode pins allow floating mode pins ? Default to Interleaved Pipeline mode

? Byte Write (BW) and/or Global Write (GW) operation ? Internal self-timed write cycle

? Automatic power-down for portable applications ? JEDEC-standard 165-bump FP-BGA package ? Pb-Free 165-bump BGA package available

Functional Description

Applications

The GS8321E18/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls

Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be

configured to count in either linear or interleave order with the

Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.

DCD Pipelined Reads

The GS8321E18/32/36E is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8321E18/32/36E operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.

Parameter Synopsis

-250-225-200-166-150-133Unit Pipeline 3-1-1-1

t KQ tCycle 2.54.0 2.74.4 3.05.0 3.56.0 3.86.6 4.07.5ns ns Curr (x18)Curr (x32/x36)

285330250290215255200235190220165195mA mA Flow Through 2-1-1-1

t KQ tCycle 5.5 6.0 6.57.07.58.5ns (x18)Curr (x32/x36)

235225

210

200

190

175

GS8321E18/32/36E-250/225/200/166/150/133

165 Bump BGA—x18 Commom I/O—Top View (Package E)

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A NC A E1B

B N

C E3BW ADSC ADV A A A

B N

C A E2NC BA CK GW G ADSP A NC B

C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA C

D NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA D

E NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA E

F NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA F

G NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA G

H FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ H

J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J

K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K

L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L

M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M

N DQPB NC V DDQ V SS NC A NC V SS V DDQ NC NC N

P NC NC A A TDI A1TDO A A A A P

R LBO A A A TMS A0TCK A A A A R

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

GS8321E18/32/36E-250/225/200/166/150/133

165 Bump BGA—x32 Common I/O—Top View (Package E)

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A NC A E1BC B

B E3BW ADS

C ADV A NC A

B N

C A E2B

D BA CK GW G ADSP A NC B

C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC C

D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D

E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E

F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F

G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G

H FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ H

J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J

K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K

L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L

M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M

N NC NC V DDQ V SS NC A NC V SS V DDQ NC NC N

P NC NC A A TDI A1TDO A A A A P

R LBO A A A TMS A0TCK A A A A R

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

GS8321E18/32/36E-250/225/200/166/150/133

165 Bump BGA—x36 Common I/O—Top View (Package E)

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A NC A E1BC B

B E3BW ADS

C ADV A NC A

B N

C A E2B

D BA CK GW G ADSP A NC B

C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C

D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D

E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E

F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F

G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G

H FT MCL NC V DD V SS V SS V SS V DD NC NC ZZ H

J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J

K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K

L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L

M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M

N DQPD NC V DDQ V SS NC A NC V SS V DDQ NC DQPA N

P NC NC A A TDI A1TDO A A A A P

R LBO A A A TMS A0TCK A A A A R

11 x 15 Bump BGA—15 mm x 17 mm Body—1.0 mm Bump Pitch

GS8321E18/32/36E 165-Bump BGA Pin Description

Symbol

Type

Description

A 0, A 1I Address field LSBs and Address Counter Preset Inputs

A I Address Inputs DQ A DQ

B DQ

C DQ

D I/O Data Input and Output pins

B A , B B , B

C , B D

I Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low

NC —No Connect

CK I Clock Input Signal; active high

BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low

E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low

ADV I Burst address counter advance enable; active l0w ADSC, ADSP

I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low

TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect Low V DD I Core power supply V SS I I/O and Core Ground V DDQ

Output driver power supply

GS8321E18/32/36E-250/225/200/166/150/133

D1Q1Q0

Counter Load

D Q

R e g i s t e r

Q Register

A0–An

LBO ADV CK ADSC ADSP GW BW E 1

FT G

Power Down Control

Memory Array

D DQx1–DQx9

Parity NC

Parity Encode

Compare

364

Note: Only x36 version shown for simplicity.

R e g i s t e r 4

B A

B B

B C

B D

GS8321E18/32/36E-250/225/200/166/150/133

GS8321E18/32/36 Block Diagram

GS8321E18/32/36E 165-Bump BGA Pin Description

Symbol

Type

Description

A 0, A 1I Address field LSBs and Address Counter Preset Inputs

A I Address Inputs DQ A DQ

B DQ

C DQ

D I/O Data Input and Output pins

B A , B B , B

C , B D

I Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active low

NC —No Connect

CK I Clock Input Signal; active high

BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low

E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active low

ADV I Burst address counter advance enable; active l0w ADSC, ADSP

I Address Strobe (Processor, Cache Controller); active low

ZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low

TMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCL —Must Connect Low V DD I Core power supply V SS I I/O and Core Ground V DDQ

Output driver power supply

GS8321E18/32/36E-250/225/200/166/150/133

Mode Pin Functions

Mode Name

Pin Name

State

Function

Burst Order Control

LBO L Linear Burst H Interleaved Burst Output Register Control

FT L Flow Through H or NC Pipeline Power Down Control

L or NC Active H

Standby, I DD = I SB

Note:

There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.

The burst counter wraps to initial state on the 5th clock.The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0]A[1:0]A[1:0]A[1:0]

1st address 000110112nd address 011011003rd address 101100014th

address

I nterleaved Burst Sequence

A[1:0]A[1:0]A[1:0]A[1:0]

1st

address 000110112nd address 010011103rd address 101100014th address

Burst Counter Sequences BPR 1999.05.18

GS8321E18/32/36E-250/225/200/166/150/133

Byte Write Truth Table

Function

B A

B B

B C

B D

Notes

Read H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4

Write all bytes

1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.

3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4.Bytes “C ” and “D ” are only available on the x36 version.

Synchronous Truth Table

Operation

Address Used

State Diagram Key 5

E 1

ADSP

ADSC

ADV

W 3

DQ 4

Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW

H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst

Current

Notes:

1.X = Don’t Care, H = High, L = Low

2.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

3.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

4.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

5.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

GS8321E18/32/36E-250/225/200/166/150/133

First Write

First Read

Burst Write

Burst Read

Deselect R W

X S i m p l e S y n c h r o n o u s O p e r a t i o n

S i m p l e B u r s t S y n c h r o n o u s O p e r a t i o n

CR R

Notes:

1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

GS8321E18/32/36E-250/225/200/166/150/133

Simplified State Diagram

First Write

First Read

Burst Write

Burst Read

Deselect

R W

X CR

R CW CR

W CW

Notes:

1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

https://www.docsj.com/doc/1110695209.html,e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS8321E18/32/36E-250/225/200/166/150/133

Simplified State Diagram with G

Absolute Maximum Ratings

(All voltages reference to V SS )

Symbol

Description

Value

Unit

V DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to 4.6

V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)

V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5W

T STG Storage Temperature –55 to 125o C T BIAS

Temperature Under Bias

–55 to 125

GS8321E18/32/36E-250/225/200/166/150/133

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3 3.6V 2.5 V V DDQ I/O Supply Voltage

V DDQ2

2.3

2.5

2.7

Notes:

1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

GS8321E18/32/36E-250/225/200/166/150/133

V DDQ3 Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

V DD Input High Voltage V IH 2.0—V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.8V 1V DDQ I/O Input High Voltage V IHQ 2.0—V DDQ + 0.3V 1,3V DDQ I/O Input Low Voltage

V ILQ

–0.3

—

0.8

1,3

Notes:

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.

V DDQ2 Range Logic Levels

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

V DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DDQ + 0.3V 1,3V DDQ I/O Input Low Voltage

V ILQ

–0.3

—

0.3*V DD

1,3

Notes:

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.

Recommended Operating Temperatures

Parameter

Symbol

Min.

Typ.

Max.

Unit

Notes

Ambient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)

T A

–40

°C

Notes:

2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

GS8321E18/32/36E-250/225/200/166/150/133

50% tKC

V SS – 2.0 V

50%V SS V IH

Undershoot Measurement and Timing

Overshoot Measurement and Timing

50% tKC

V DD + 2.0 V

50%V DD

V IL

Capacitance

o C, f = 1 MH Z , V DD Parameter

Symbol

Test conditions

Typ.

Max.

Unit

Input Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/O

V OUT = 0 V

Note:

These parameters are sample tested.AC Test Conditions

Parameter

Conditions

Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference level

V DDQ /2Output load

Fig. 1

Notes:

1.Include scope and jig capacitance.

2.Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3.Device is deselected as defined by the Truth Table.

V DDQ/2

50?30pF *

Output Load 1

* Distributed Test Jig Capacitance

(T A = 25= 2.5 V)

D C

E l e c t r i c a l C h a r a c t e r i s t i c s

P a r a m e t e r

S y m b o l T e s t C o n d i t i o n s

M i n M a x

I n p u t L e a k a g e C u r r e n t (e x c e p t m o d e p i n s )

I I L

V I N = 0 t o V D D –1 u A

1 u A

Z Z I n p u t C u r r e n t

I I N 1

V D D ≥ V I N ≥ V I H

0 V ≤ V I N ≤ V I H

–1 u A –1 u A

1 u A 100 u A F T I n p u t C u r r e n t

I I N 2

V D D ≥ V I N ≥ V I L

0 V ≤ V I N ≤ V I L

–100 u A –1 u A

1 u A 1 u A

O u t p u t L e a k a g e C u r r e n t

I O L

O u t p u t D i s a b l e , V O U T = 0 t o V D D

–1 u A

1 u A

O u t p u t H i g h V o l t a g e

V O H 2

I O H = –8 m A , V D D Q = 2.375 V

1.7 V

—O u t p u t H i g h V o l t a g e

V O H 3

I O H = –8 m A , V D D Q = 3.135 V

2.4 V

—O u t p u t L o w V o l t a g e

V O L

I O L = 8 m A

—0.4 V GS8321E18/32/36E-250/225/200/166/150/133

Operating Currents

Parameter

Test Conditions

Mode

Symbol

-250

-225-200-166-1500to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40to 85°C 0 to 70°C –40to 85°C 0 to 70°C –40to 85°C Operating Current

Device Selected; All other inputs ≥V IH o r ≤ V IL Output open

(x32/x36)

Pipeline

I DD I DDQ 28050290502454525545215402254020035210351903020030Flow Through I DD I DDQ 21025220252002521025190202002018020190201702018020(x18)

Pipeline

I DD I DDQ 26025270252252523525195202052018020190201702018020Flow Through

I DD I DDQ 19015200151801519015170151801516015170151501516015Standby Current

ZZ ≥ V DD – 0.2 V

—

Pipeline

I SB 40504050405040504050Flow Through I SB 40504050405040504050Deselect Current

Device Deselected; All other inputs ≥ V IH or ≤ V IL

—

Pipeline I DD 75807580707570756570Flow Through I DD

GS8321E18/32/36E-250/225/200/166/150/133

1.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.

2.All parameters listed are worst case scenario.

AC Electrical Characteristics

Parameter Symbol -250-225-200-166-150-133Unit

Min Max Min Max Min Max Min Max Min Max Min Max Flow Through

Clock Cycle Time tKC 5.5— 6.0— 6.5—7.0—7.5—8.5—ns Clock to Output Valid

tKQ — 5.5— 6.0— 6.5—7.0—7.5—8.5ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z

tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5— 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3— 1.3— 1.5— 1.7—ns Clock LOW Time tKL 1.5— 1.5— 1.5— 1.5— 1.7—2—ns Clock to Output in

High-Z tHZ 1 1.5 2.5 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 2.7— 3.2— 3.5— 3.8— 4.0ns G to output in Low-Z tOLZ 10—0—0—0—0—0—ns G to output in High-Z tOHZ 1— 2.5— 2.7— 3.0— 3.0— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—1—ns ZZ recovery

tZZR

—

ns GS8321E18/32/36E-250/225/200/166/150/133

Notes:

1.These parameters are sampled and are not 100% tested.

2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

GS8321E18/32/36E-250/225/200/166/150/133

Pipeline Mode Timing (DCD)

Begin Read A Cont Deselect Deselect Write B

Read C Read C+1Read C+2Read C+3Cont Deselect Deselect

tHZ

tKQX

tKQ

tLZ

tOHZ

tOE

tH tS

tKC

tKL tKH

Q(A)

D(B)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Hi-Z

Deselected with E1

E2 and E3 only sampled with ADSC

ADSC initiated read

CK ADSP

ADSC

ADV

Ao–An

Ba–Bd

E3G

DQa–DQd

GS8321E18/32/36E-250/225/200/166/150/133

Flow Through Mode Timing (DCD)

Begin Read A Cont

Deselect Write B Read C Read C+1Read C+2Read C+3Read C Deselect

tHZ

tKQX tLZ

tH tS

tOHZ

tOE tKQ

tS tH

tH tS

tS tH

tS tH tS

tH tS tH

tS tKC

tKL tKH

Q(A)

D(B)

Q(C)

Q(C+1)

Q(C+2)

Q(C+3)

Q(C)

E2 and E3 only sampled with ADSP and ADSC

E1 masks ADSP

ADSC initiated read

Deselected with E1

E1 masks ADSP

Fixed High

CK ADSP

ADSC

ADV

Ao–An

Ba–Bd

E3G

DQa–DQd