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CAT1024ZI-28-GT3中文资料

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

Supervisory Circuits with I 2

C Serial 2k-bit CMOS EEPROM and Manual Reset

FEATURES

Precision Power Supply Voltage Monitor — 5V, 3.3V and 3V systems — Five threshold voltage options Active High or Low Reset

— Valid reset guaranteed at V CC = 1V 400kHz I 2C Bus 2.7V to 5.5V Operation Low power CMOS technology 16-Byte Page Write Buffer

Built-in inadvertent write protection — WP pin (CAT1025)

1,000,000 Program/Erase cycles Manual Reset Input 100 year data retention

Industrial and extended temperature ranges Green packages available with NiPdAu Lead finished

For Ordering Information details, see page 19.

DESCRIPTION

The CAT1024 and CAT1025 are complete memory and supervisory solutions for microcontroller-based systems. A 2k-bit serial EEPROM memory and a system power supervisor with brown-out protection are integrated together in low power CMOS techno–logy. Memory interface is via a 400kHz I 2C bus. The CAT1025 provides a precision V CC sense circuit and two open drain outputs: one (RESET) drives high

and the other (RESET

ˉˉˉˉˉˉ) drives low whenever V CC falls below the reset threshold voltage. The CAT1025 also has a Write Protect input (WP). Write operations are disabled if WP is connected to a logic high.

The CAT1024 also provides a precision V CC sense

circuit, but has only a RESET

ˉˉˉˉˉˉ output and does not have a Write Protect input.

The power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. Five reset threshold voltages support 5V, 3.3V and 3V systems. If power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, ASIC or peripherals from operating. Reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. With both active high and low reset signals, interface to microcontrollers and other ICs is simple. In addition,

the RESET

ˉˉˉˉˉˉ pin or a separate input, MR ˉˉˉ, can be used as an input for push-button manual reset capability. The CAT1024/25 memory features a 16-byte page. In addition, hardware data protection is provided by a V CC sense circuit that prevents writes to memory whenever V

CC falls below the reset threshold or until V CC reaches the reset threshold during power up. Available packages include an 8-pin DIP and a surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin MSOP packages. The TDFN package thick-ness is 0.8mm maximum. TDFN footprint is 3x3mm.

CAT1024, CAT1025 Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

BLOCK DIAGRAM

THRESHOLD VOLTAGE OPTION

Part Dash Number Minimum Threshold Maximum Threshold

-45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70

PIN CONFIGURATION

DIP Package (L ) SOIC Package (W ) TSSOP Package (Y ) MSOP Package (Z )

MR ˉˉˉ 1 8 V CC RESET

ˉˉˉˉˉˉ 2 7 NC NC 3 6 SCL

V SS 4

5 SDA

CAT1024

MR ˉˉˉ 1 8 V CC RESET

ˉˉˉˉˉˉ 2 7 WP RESET 3 6 SCL

V SS 4

5 SDA

CAT1025

(Bottom View)

TDFN Package: 3mm x 3mm 0.8mm maximum height - (ZD4)

V CC

MR ˉˉˉ NC RESET ˉˉˉˉˉˉ SCL NC

SDA V SS

V CC

MR ˉˉˉ WDI RESET ˉˉˉˉˉˉ SCL RESET

SDA V

EXTERNA L LO AD

SCL

RESET*

* CAT1025 Only

RESE T

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

PIN DESCRIPTION

RESET/RESET

ˉˉˉˉˉˉ: RESET OUTPUTs (RESET CAT1025 Only)

These are open drain pins and RESET

ˉˉˉˉˉˉ can be used as a manual reset trigger input. By forcing a reset condition on the pin the device will initiate and maintain a reset condition. The RESET pin must be connected through a pull-down resistor, and the RESET ˉˉˉˉˉˉ pin must be connected through a pull-up resistor.

SDA: SERIAL DATA ADDRESS

The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. SCL: SERIAL CLOCK Serial clock input.

MR ˉˉˉ: MANUAL RESET INPUT

Manual Reset input is a debounced input that can be connected to an external source for Manual Reset. Pulling the MR input low will generate a Reset

condition. Reset outputs are active while MR

ˉˉˉ input is low and for the reset timeout period after MR

ˉˉˉ returns to high. The input has an internal pull up resistor. WP (CAT1025 Only): WRITE PROTECT INPUT

When WP input is tied to V SS or left unconnected write operations to the entire array are allowed. When tied to V CC , the entire array is protected. This input has an internal pull down resistor.

PIN FUNCTION

Pin Name Function NC No Connect

RESET ˉˉˉˉˉˉ Active Low Reset Input/Output V SS Ground

SDA Serial Data/Address SCL Clock Input

RESET Active High Reset Output

(CAT1025 only) V CC Power Supply

WP Write Protect (CAT1025 only) MR ˉˉˉ

Manual Reset Input

OPERATING TEMPERATURE RANGE

Industrial

-40oC to 85oC

Extended -40oC to 125oC

CAT10XX FAMILY OVERVIEW

Device Manual Reset Input Pin

Watchdog Watchdog Monitor Pin Write

Protection

Pin Independent

Auxiliary Voltage Sense

RESET: Active High and LOW

EEPROM

CAT1021 SDA

2k CAT1022

SDA

2k CAT1023 WDI

2k CAT1024

2k CAT1025

2k CAT1026

CAT1027

WDI

2k For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.

CAT1024, CAT1025

Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

ABSOLUTE MAXIMUM RATINGS (1)Parameters

Ratings Units

Temperature Under Bias –55 to +125 oC Storage Temperature

–65 to +150 oC Voltage on any Pin with Respect to Ground (2) –2.0 to V CC + 2.0 V V CC with Respect to Ground

–2.0 to 7.0

V Package Power Dissipation Capability (T A = 25°C) 1.0 W Lead Soldering Temperature (10 secs)

300

Output Short Circuit Current (3) 100 mA D.C. OPERATING CHARACTERISTICS

V CC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified. Symbol Parameter Test Conditions Min Typ Max Units I LI Input Leakage Current V IN = GND to Vcc -2 10 μA I LO Output Leakage Current V IN = GND to Vcc -10

μA

I CC1 Power Supply Current (Write) f SCL = 400kHz V CC = 5.5V 3 mA

I CC2

Power Supply Current (Read)

f SCL = 400kHz V CC = 5.5V 1 mA

I SB Standby Current Vcc = 5.5V,

V IN = GND or Vcc 40 μA V IL (4) Input Low Voltage -0.5 0.3 x Vcc V V IH (4) Input High Voltage

0.7 x Vcc

Vcc + 0.5

V OL Output Low Voltage

(SDA, RESET ˉˉˉˉˉˉ) I OL = 3mA V CC = 2.7V 0.4 V V OH

Output High Voltage (RESET)

I OH = -0.4mA V CC = 2.7V Vcc - 0.75

CAT102x-45 (V CC = 5.0V) 4.50 4.75 V CAT102x-42 (V CC = 5.0V)

4.25 4.50 CAT102x-30

(V CC = 3.3V) 3.00 3.15 CAT102x-28 (V CC = 3.3V) 2.85 3.00 V TH Reset Threshold

CAT102x-25 (V CC = 3.0V)

2.55 2.70 V RVALID Reset Output Valid V CC Voltage 1.00 V V RT (5)

Reset Threshold Hysteresis

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V CC +0.5V, which may overshoot to V CC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) V IL min and V IH max are reference values only and are not tested.

(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

CAPACITANCE

T A = 25oC, f = 1.0MHz, V CC = 5V Symbol Test

Test Conditions

Max Units C OUT (1) Output Capacitance V OUT = 0V 8 pF C IN (1) Input Capacitance

V IN = 0V

AC CHARACTERISTICS

V CC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified. Memory Read & Write Cycle (2) Symbol Parameter Min Max Units f SCL Clock Frequency 400 kHz

t SP Input Filter Spike Suppression (SDA, SCL) 100 ns t LOW Clock Low Period 1.3 μs t HIGH Clock High Period

0.6 μs t R (1) SDA and SCL Rise Time 300 ns t F (1) SDA and SCL Fall Time 300 ns t HD; STA Start Condition Hold Time

0.6 μs t SU; STA Start Condition Setup Time (for a Repeated Start) 0.6 μs t HD; DAT Data Input Hold Time 0 ns t SU; DAT Data Input Setup Time 100 ns t SU; STO Stop Condition Setup Time 0.6 μs t AA SCL Low to Data Out Valid 900 ns t DH Data Out Hold Time

50 ns t BUF (1) Time the Bus must be Free Before a New Transmission Can Start 1.3 μs t WC (3)

Write Cycle Time (Byte or Page)

Notes:

(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (2) Test Conditions according to “AC Test Conditions” table.

(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

CAT1024, CAT1025

Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

RESET CIRCUIT AC CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units

t PURST Power-Up Reset Timeout Note 2 130 200 270 ms t RDP V TH to RESET Output Delay Note 3 5 μs t GLITCH V CC Glitch Reject Pulse Width Note 4, 5 30 ns MR Glitch Manual Reset Glitch Immunity Note 1 100 ns t MRW MR Pulse Width

Note 1 5 μs t MRD

MR Input to RESET Output Delay

Note 1

μs

POWER-UP TIMING (5), (6)

Symbol Parameter

Test Conditions Min Typ Max Units t PUR Power-Up to Read Operation 270 ms t PUW

Power-Up to Write Operation

270

AC TEST CONDITIONS

RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Max Units N END (5) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte T DR (5) Data Retention MIL-STD-883, Test Method 1008 100 Years V ZAP (5)

ESD Susceptibility

MIL-STD-883, Test Method 3015

2000 Volts I LTH (5)(7) Latch-Up

JEDEC Standard 17

100

Notes:

(1) Test Conditions according to “AC Test Conditions” table.

(2) Power-up, Input Reference Voltage V CC = V TH , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (3) Power-Down, Input Reference Voltage V CC = V TH , Reset Output Reference Voltage and Load according to “AC Test Conditions” Table (4) V CC Glitch Reference Voltage = V THmin ; Based on characterization data

(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (6) t PUR and t PUW are the delays required from the time V CC is stable until the specified memory operation can be initiated. (7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V CC + 1V.

Parameter

Test Conditions Input Pulse Voltages 0.2V CC to 0.8V CC

Input Rise and Fall Times 10ns Input Reference Voltages 0.3V CC , 0.7V CC

Output Reference Voltages 0.5V CC

Output Load

Current Source: I OL = 3mA; C L = 100pF

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

DEVICE OPERATION

Reset Controller Description

The CAT1024/25 precision RESET controllers ensure correct system operation during brownout and power up/down conditions. They are configured with open drain RESET outputs.

During power-up, the RESET outputs remain active until V CC reaches the V TH threshold and will continue driving the outputs for approximately 200ms (t PURST ) after reaching V TH . After the t PURST timeout interval, the device will cease to drive the reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/down resistors.

During power-down, the RESET outputs will be active

when V CC falls below V TH . The RESET

ˉˉˉˉˉˉ output will be valid so long as V CC is >1.0V (V RVALID ). The device is designed to ignore the fast negative going V CC transi-ent pulses (glitches).

Reset output timing is shown in Figure 1.

Manual Reset Operation

The RESET

ˉˉˉˉˉˉ pin can operate as reset output and manual reset input. The input is edge triggered; that

is, the RESET

ˉˉˉˉˉˉ input will initiate a reset timeout after detecting a high to low transition.

When RESET

ˉˉˉˉˉˉ I/O is driven to the active state, the 200ms timer will begin to time the reset interval. If external reset is shorter than 200ms, Reset outputs will remain active at least 200ms.

The CAT1024/25 also have a separate manual reset

input. Driving the MR

ˉˉˉ input low by connecting a pushbutton (normally open) from MR

ˉˉˉ pin to GND will generate a reset condition. The input has an internal

pull up resistor.

Reset remains asserted while MR

ˉˉˉ is low and for the Reset Timeout period after MR

ˉˉˉ input has gone high. Glitches shorter than 100ns on MR

ˉˉˉ input will not ge-nerate a reset pulse. No external debouncing circuits

are required. Manual reset operation using MR

ˉˉˉ input is shown in Figure 2.

Hardware Data Protection

The CAT1024/25 supervisors have been designed to solve many of the data corruption issues that have long been associated with serial EEPROMs. Data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data.

Whenever the device is in a Reset condition, the embedded EEPROM is disabled for all operations, including write operations. If the Reset output(s) are active, in progress communications to the EEPROM are aborted and no new communications are allowed. In this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. An internal write cycle initiated before the Reset condition can be successfully finished if there is enough time (5ms) before V CC reaches the minimum value of 2V. In addition, the CAT1025 includes a Write Protection Input which when tied to V CC will disable any write operations to the device.

CAT1024, CAT1025

Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Figure 1. RESET Output Timing

Figure 2: MR ˉˉˉ Operation and Timing

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

EMBEDDED EEPROM OPERATION

The CAT1024 and CAT1025 feature a 2-kbit embedded serial EEPROM that supports the I 2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated.

I 2

C BUS PROTOCOL

The features of the I 2C bus protocol are defined as follows:

(1) Data transfer may be initiated only when the bus

is not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START CONDITION

The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT1024/25 monitors the SDA and SCL lines and will not respond until this condition is met. STOP CONDITION

A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.

After the Master sends a START condition and the slave address byte, the CAT1024/25 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT1024/25 then perform a Read or

Write operation depending on the R/W

ˉˉ bit.

Figure 3. Bus Timing

Figure 4. Write Cycle Timing

SCL

SDA IN

SDA OUT

STOP

CONDITION

START

CONDITION

ADDRESS

SCL

SDA

CAT1024, CAT1025 Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

ACKNOWLEDGE

After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.

The CAT1024/25 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte.

When the CAT1024/25 begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1024/25 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmis–sion and waits for a STOP condition. WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the START condition and the slave address information

(with the R/W

ˉˉ bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the device. After receiving another acknow-ledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1024/25 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device.

Figure 5. Start/Stop Timing

Figure 6. Acknowledge Timing

Figure 7: Slave Address Bits

START BIT

SDA

STOP BIT

SCL

ACKNOWLEDGE

START

SCL FROM MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT FROM RECEIVER

1010000R/W

Default Configuration

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

Page Write

The CAT1024/25 writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, the CAT1024/25 will respond with an acknowledge and internally increment the lower order address bits by one. The high order bits remain unchanged. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around,’ and previously transmitted data will be overwritten.

When all 16 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT1024/25 in a single write cycle.

Figure 8. Byte Write Timing

Figure 9: Page Write Timing

BYTE ADDRESS

SLAVE ADDRESS S

C K

A C K

DA T A

A C K

S T O P P

BUS ACTIVITY:

MASTER

SDA LINE

S T A R T BUS ACTIVITY:

MASTER

SDA LINE

BYTE C K

C K

S T

C K

S T A R SLAVE

CAT1024, CAT1025

Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

Acknowledge Polling

Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write opration, the CAT1024/25 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the device is still busy with the write operation, no ACK will be returned. If a write operation has completed, an ACK will be returned and the host can then proceed with the next read or write operation.

WRITE PROTECTION PIN (WP)

The Write Protection feature (CAT1025 only) allows the user to protect against inadvertent memory array programming. If the WP pin is tied to V CC , the entire memory array is protected and becomes read only. The CAT1025 will accept both slave and byte addre-sses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. READ OPERATIONS

The READ operation for the CAT1024/25 is initiated in the same manner as the write operation with one exception,

the R/W

ˉˉ bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ.

Figure 10. Immediate Address Read Timing

SCL SDA 8TH BI T STOP

NO ACK

DATA OUT

SLAVE ADDRESS

A C K

DA TA

N O A C K S T O P P

BUS ACTIVIT Y:

MASTER

SDA LINE

S T A R T

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

Immediate/Current Address Read

The CAT1024 and CAT1025 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. For N = E = 255, the counter will wrap around to zero and continue to clock out valid data. After the CAT1024/1025 receives its slave

address information (with the R/W

ˉˉ bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read

Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After the CAT1024 and CAT1025 acknowledges, the Master device sends the START condition and the slave

address again, this time with the R/W

ˉˉ bit set to one. The CAT1024 and CAT1025 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT1024 and CAT1025 sends the inital 8-bit byte requested, the Master will responds with an acknowledge which tells the device it requires more data. The CAT1024 and CAT1025 will continue to output an 8-bit byte for each acknowledge, thus sending the STOP condition.

The data being transmitted from the CAT1024 and CAT1025 is sent sequentially with the data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT1024 and CAT1025 address bits so that the entire memory array can be read during one operation.

Figure 11. Selective Read Timing

Figure 12. Sequential Read Timing

SLAVE ADDRESS

A C K

N O A C K

S T O P P

BUS ACTIVITY:

MASTER

SDA LINE

S T A R T BYTE ADDRESS (n)

A C K

DA T A n

SLAVE ADDRESS

A C K

S T A R

T BUS ACTIVITY:

MASTER

SDA LINE

C K

S T O O A C K

C K

SLAVE

CAT1024, CAT1025 Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

PACKAGE OUTLINES

8-LEAD 300 MIL WIDE PLASTIC DIP (L)

Notes :

(1) All dimensions are in millimeters.

(2) Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.

SYMBOL

A A1b b2D E E1e e

B L

MIN 0.380.369.027.626.09 6.357.872.92

3.81

NOM 0.46 1.771.147.872.54 BSC

MAX 4.57A2 3.05 3.810.56c 0.210.260.3510.168.257.119.65

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

8-LEAD 150 MIL SOIC (W)

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC specification MS-012 dimensions.

SYMBOL

A1A b C D E E1h L MIN 0.101.350.334.805.803.80

0.250.40NOM 0.250.19MAX 0.251.750.515.006.204.00

e 1.27 BSC

0.501.27q1

0°

8°

CAT1024, CAT1025

Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

8-LEAD TSSOP (V)

Notes:

(1) All dimensions are in millimeters. (2) Complies with JEDEC Standard MO-153

SEE DETAIL A

SYMBOL A A1A2b c D E E1e L q1

MIN 0.050.800.092.906.30 6.44.300.00

8.00

NOM 0.90

0.300.19 3.004.400.60

0.750.50MAX 1.200.151.050.203.106.504.500.65 BSC

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

8-LEAD MSOP (Z)

Notes:

(1) All dimensions are in millimeters.

(2) This part is compliant with JEDEC Specification MO-187 Variations AA.

SYMBOL

MIN NOM MAX A 1.1

A10.050.100.15A20.750.850.95b 0.28

0.33

0.38

c D 2.90 3.00 3.10E 4.80 4.90 5.00E1 2.90

3.00 3.10

e 0.65BSC

L 0.350.450.55

L1L2?

0o6o

CAT1024, CAT1025

Doc. No. 3008 Rev. N

? 2007 Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

TDFN 3 x 3 PACKAGE (ZD4)

Notes: (1) All dimentions in mm. Angels in degrees. (2) Complies to JEDEC MO-229 / WEEC. (3) Coplanarity shall not exceed 0.10mm. (4) Warpage shall not exceed 0.10mm.

(5)

Package lenght / package width are considered as special characteristic(s).

CAT1024, CAT1025

? 2007 Catalyst Semiconductor, Inc.

Doc. No. 3008 Rev. N

Characteristics subject to change without notice

EXAMPLE OF ORDERING INFORMATION

Notes: (1)

All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin.

(3) The device used in the above example is a CAT1024WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel). (4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office. (5) TDFN not available in NiPdAu (–G) version.

Ordering Part Number – CAT1024xx Ordering Part Number – CAT1025xx

CAT1024LI-45 CAT1024ZI-45 CAT1025LI-45 CAT1025ZI-45 CAT1024LI-42 CAT1024ZI-42 CAT1025LI-42 CAT1025ZI-42 CAT1024LI-30 CAT1024ZI-30 CAT1025LI-30

CAT1025ZI-30 CAT1024LI-28 CAT1024ZI-28 CAT1025LI-28

CAT1025ZI-28 CAT1024LI-25 CAT1024ZI-25 CAT1025LI-25

CAT1025ZI-25 CAT1024WI-45 CAT1024ZD4I-45 CAT1025WI-45 CAT1025ZD4I-45 CAT1024WI-42 CAT1024ZD4I-42 CAT1025WI-42 CAT1025ZD4I-42 CAT1024WI-30 CAT1024ZD4I-30 CAT1025WI-30 CAT1025ZD4I-30 CAT1024WI-28 CAT1024ZD4I-28 CAT1025WI-28 CAT1025ZD4I-28 CAT1024WI-25 CAT1024ZD4I-25 CAT1025WI-25 CAT1025ZD4I-25 CAT1024YI-45 CAT1025YI-45 CAT1024YI-42 CAT1025YI-42 CAT1024YI-30 CAT1025YI-30 CAT1024YI-28 CAT1025YI-28 CAT1024YI-25

CAT1025YI-25

Prefix Device # Suffix

REVISION HISTORY

Date Rev. Reason

11/07/2003 I Eliminated Automotive

temperature range 4/12/2004 J

Eliminated data sheet designation Updated Reel Ordering Information

11/01/2004 K Changed SOIC package designators

Eliminated 8-pad TDFN (3x4.9mm) package

Added package outlines 11/04/2004 L Update Pin Configuration

11/11/2004 M

Update Feature Update Description

Update DC Operating Characteristic Update AC Characteristics 02/02/2007 N

Update Example of Ordering Information

Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Document No: 3008 Fax: 408.542.1200 Revision: N

https://www.docsj.com/doc/d711081349.html, Issue date: 02/02/07

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Beyond Memory?, DPP?, EZDim?, MiniPot?, and Quad-Mode?

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.

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Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.

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