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PI6C185-01B中文资料

PI6C185-01B Precision 1-5 Clock Buffer

Pin Configuration

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Features

High-speed, low-noise non-inverting 1-5 buffer

Switching speed up to 140 MHz

Supports up to two SODIMMs

Low skew (<250ps) between any two output clocks

I2C Serial Configuration interface

Multiple V DD, V SS pins for noise reduction

3.3V power supply voltage

16-pin TSSOP (L) and QSOP (Q) packages

Description

The PI6C185-01B, a high-speed low-noise 1-5 non-inverting buffer

designed for SDRAM clock buffer applications, is intended to be

used with the PI6C10X clock generator for Intel Architecture-based

Mobile systems.

At power up, all SDRAM outputs are enabled and active. The I2C

Serial control may be used to individually activate/deactivate any

of the five output drivers.

Note:

Purchase of I2C components from Pericom conveys a license to

use them in an I2C system as defined by Philips.

Vss4

BUF_IN5

SDRAM1

SDATA7

Vss

Vdd

Vss

Vdd

SDRAM2

Vss

SCLK

Vdd

SDRAM0

SDRAM3

SDRAM4

16-Pin

L, Q

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Precision 1-5 Clock Buffer

Pin Description

PI6C185-01B Serial Configuration Map

Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

Note:

Inactive means outputs are held LOW and are disabled from switching

PI6C185-01B I 2C Address Assignment

6A 5A 4A 3A 2A 1A 0A W /R 1

t i B #n i P n

o i t p i r c s e D 7t i B 21)e v i t c a n I /e v i t c A (3M A R D S 6t i B 11)e v i t c a n I /e v i t c A (2M A R D S 5t i B -)0o t e z i l a i t i n I (C N 4t i B -)0o t e z i l a i t i n I (C N 3t i B -)0o t e z i l a i t i n I (C N 2t i B -)0o t e z i l a i t i n I (C N 1t i B 3)e v i t c a n I /e v i t c A (1M A R D S 0

t i B 2

)

e v i t c a n I /e v i t c A (0M A R D S Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

t i B #n i P n

o i t p i r c s e D 7t i B -)0o t e z i l a i t i n I (C N 6t i B -)0o t e z i l a i t i n I (C N 5t i B -)0o t e z i l a i t i n I (C N 4t i B -)0o t e z i l a i t i n I (C N 3t i B -)0o t e z i l a i t i n I (C N 2t i B -)0o t e z i l a i t i n I (C N 1t i B -)0o t e z i l a i t i n I (C N 0

t i B 5

e v i t c a n I /e v i t c A (4M A R D S n

i P l

a n g i S e

p y T y

t Q n

o i t p i r c s e D 5

1,21,11,3,2]4.0[M A R D S I 5s t u p t u O k c o l C d e r e f f u B 5N I _F U B I 1t

u p n I r e f f u B k c o l C 7A T A D S O /I 1I r o f a t a D l a i r e S 2p u -l l u p l a n r e t n i ,e c a f r e t n i C 8K L C S I 1I r o f k c o l C l a i r e S 2p u -l l u p l a n r e t n i ,e c a f r e t n i C 61,31,6,1V D D r e w o P 4y l p p u S r e w o P V 3.34

1,01,9,4V S

S d

n u o r G 4

n u o r G

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Precision 1-5 Clock Buffer

l o b m y S r e t e m a r a P n

o i t i d n o C t s e T .

n i M .

p y T .x a M s

t i n U I D D t n e r r u C y l p p u S z H M 0=N I _F U B 3

A m I D D t n e r r u C y l p p u S z H M 66.66=N I _F U

B 07I D D t n e r r u

C y l p p u S z H M 0.001=N I _F U B 021I D

D t

n e r r u C y l p p u S z

H M 3.331=N I _F U B 0

02The I 2C interface permits individual enable/disable of each clock output and test mode enable.

The PI6C185-01B, a slave receiver device, cannot be read back.Sub addressing is not supported. To change one of the control bytes, all preceding bytes must be sent

Every byte put on the SDATA line must be 8-bits long (MSB first),followed by an acknowledge bit generated by the receiving device.

During normal data transfers SDATA changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a “start” condition. A LOW to HIGH transition on SDATA while SCLK is HIGH is a “stop” condition and indicates the end of a data transfer cycle.

Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the device’s own address is detected, PI6C185-01B generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected.

Following acknowledgement of the address byte (0D2H), two more bytes must be sent:

1. “Command Code” byte &

2. “Byte Count” byte.Although the data bits on these two bytes are “don’t care,” they must be sent and acknowledged.

2-Wire I 2C Control

Storage Temperature...................................... 65°C t o +150°C Ambient Temperature with Power Applied........ 0°C to +70°C 3.3V Supply Voltage to Ground Potential........... 0.5V t o +4.6V DC Input Voltage .............................................. 0.5V t o +4.6V

Note:

Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Supply Current (V DD = +3.465V, C LOAD = Max.)

Maximum Ratings

(Above which the useful life may be impaired.For user guidelines, not tested.)

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Precision 1-5 Clock Buffer

SDRAM Clock Buffer Operating Specification

AC Timing

DC Operating Specifications (V DD = +3.3V ±5%, T A = 0°C –70°C)

l o b m y S r

e t e m a r a P n o i t i d n o C .n i M .p y T .x a M s

t i n U I N I M H O t n e r r u c p u -l l u P V T U O V 0.2=0

4 A

m I X A M H O t n e r r u c p u -l l u P V T U O V 531.3=6

3I N I M L O t n e r r u c n w o d -l l u P V T U O V 0.1=0

4I X

A M L O t

n e r r u c n w o d -l l u P V T U O V

4.0=83t H R M A R D S y l n o M A R D S e t a r e g d e e s i r t u p t u O V 4.2-V 4.0@%5±V 3.3

5.14

s n /V t H F M A R D S y

l n o M A R D S e t a r e g d e l l a f t u p t u O V

4.0-V 4.2@%5±V 3.3

5.14

l o b m y S r

e t e m a r a P n

o i t i d n o C .

n i M .

x a M s

t i n U e g a t l o V t u p n I V H I e g a t l o V h g i H t u p n I V D

D 0.2V D D 3.0+V V L I e g a t l o V w o L t u p n I V S S 3.0 8.0I L

I t

n e r r u C e g a k a e L t u p n I V <0N I V

D 5

+μA

V D D %5±V 3.3=V H O e g a t l o V h g i H t u p t u O I H O A m 1-=4

.2V

V L

O e

g a t l o V w o L t u p t u O I L O A

m 1=4

.0C N I e c n a t i c a p a C n i P t u p n I 5F p C T U O e c n a t i c a p a C s n i p t u p t u O 6L N I P e c n a t c u d n I n i P 7H n T A

r u t a r e p m e T t n e i b m A w

o l f r i A o N 0

ol o b m y S r

e t e m a r a P z H M 66z H M 001z H M 331s

t i n U .n i M .x a M .n i M .x a M .n i M .x a M t P K D S d o i r e p K L C M A R D S 0.515

.510.015

.015.78

.7s

n t H K D S e m i t h g i h K L C M A R D S 6.53.30.1t L K D S e m i t w o l K L C M A R D S 3.51.30.1t E S I R D S e m i t e s i r K L C M A R D S 5.10.45.10.45.10.4s

n /V t L L A F D S e m i t l l a f K L C M A R D S 5.10.45.10.45.10.4t H L P y a l e d p o r p H L r e f f u B M A R D S 0.15.50.15.50.15.5s

n t L H P y a l e d p o r p L H r e f f u B M A R D S 0.15.50.15.50.15.5t L Z P t ,H Z P y a l e d e l b a n E r e f f u B M A R D S 0.10.80.10.80.10.8t Z L P t ,Z H P y a l e d e l b a s i D r e f f u B M A R D S 0.10.80.10.80.10.8e l c y C y t u D V

5.1t a d e r u s a e M 5

4555

455%t W

K S D S w

e k S t u p t u O o t t u p t u O M A R D S 0520520

52s

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Precision 1-5 Clock Buffer

Figure 1. Clock Waveforms

Notes:

1.Maximum rise/fall times are guaranteed at maximum specified load.

2.Minimum rise/fall times are guaranteed at minimum specified load.

3.Rise/fall times are specified with pure capacitive load as shown.Testing is done with an additional 500? resistor in parallel.

Minimum and Maximum Expected Capacitive Loads

Design Guidelines to Reduce EMI

1.Place R S series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. R S Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values.

2.Minimize the number of “vias” of the clock traces.

3.Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2).

4.Position clock signals away from signals that go to any cables or any external connectors.

k c o l C d a o L n i M d

a o L x a M s t i n U s

e t o N M

A R D S 5

p n

o i t a c i f i c e p S M M I D M A R D S

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Precision 1-5 Clock Buffer

Pericom Semiconductor Corporation

2380 Bering Drive ?San Jose, CA 95131 ? 1-800-435-2336?Fax (408) 435-1100 ?https://www.docsj.com/doc/c816127919.html,

16-Pin TSSOP (L) Package Ordering Information

Figure 2. Design Guidelines

/P n

o i t p i r c s e D L B 10-581C 6I P e g a k c a P P O S S T Q

B 10-581

C 6I P e

g a k c a P P O S Q

16-Pin QSOP (Q) Package