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Error Canceling Low V oltage SAR-ADC

by

Jianping Wen

A Thesis

submitted to

Oregon State University

in partial ful?llment of

the requirements for the

degree of

Master of Science

Completed July26,2000

Commencement June2001

ACKNOWLEDGMENTS

I would like to express my sincere and deep appreciation to my academic advi-sors,Dr.Gabor C.Temes and Dr.Un-Ku Moon,for the research project and excellent academic environment they provided for me.I have been honored and privileged to have worked under their supervision.Without their warm encouragement and aca-demic guidance as well as their generous support,it would be impossible for me to complete the work presented in this thesis.

Special thanks are extended to Dr.Byung-Moo Min for his competent expertise in circuit design that greatly helped me in the transistor level implementations of the designed A/D converter.The author also wants to thank Dr.Kyoung-Rok Cho for the valuable discussion on digital circuit design.

I would like to express my appreciation to Dr.John T.Stonick for many enlight-ening discussions and comments on my research during our regular weekly research group meetings.

I also would like to thank Prof.Robert J.Schultz for taking time out of his busy schedule to serve as the Graduate Council Representative of my committee.

Many thanks,also,to Mr.Jos′e Silva for his kind help with his wonderful skills in various CAD tools.Without his help,I could not be able to complete my thesis now but I would still be exploring the details of those necessary CAD tools for my design.

I wish to thank my colleagues in our research group,Mr.Tetsuya Kajita,Mr. Mustafa Keskin,Dr.Peter Kiss and Mr.Dong-Yang Chang,for discussions on vari-ous technical issues on this research project.

I wish to express my thanks to National Semiconductor Corporation for their ?nancial support to this project and their facilities for fabricating the prototype chip of this thesis.

Finally,I would like to dedicate this thesis to my wife,Lichun Jia,and my daugh-ter,Xueyin Wen.I would not be able to?nish this thesis without the support of my loving family.

TABLE OF CONTENTS

Page Chapter1:Introduction1 1.1Motivation (1)

1.2Thesis Structure (3)

Chapter2:Mismatch Error Cancellation Algorithm5 2.1Conceptual Operation of a Successive Approximation ADC (5)

2.2Circuit Non-idealities (6)

2.3A Novel Capacitor Mismatch Error Cancellation Technique for Switched

Capacitor SAR–ADC (7)

2.4Improvement of Mismatch Error Cancellation Algorithm (16)

Chapter3:Predictive Correlated Triple Sampling(CTS)22 3.1Introduction (22)

3.2Theoretical Analysis of The Switched Capacitor SAR–ADC (24)

3.2.1Initial Charges Introduced by Sampling (24)

3.2.2Charge Domain Analysis of Normal Converting Cycles (27)

3.2.3Calculation of Harmonic Distortion after CDS Compensation31

3.2.4Discussion and Conclusion (32)

3.3Improvement of Predictive CDS in SC SAR–ADC (33)

3.4Veri?cation of Predictive CTS by SWITCAP Simulations of SAR–

ADC (36)

Chapter4:Design of A1.8V Switched Capacitor SAR–ADC40 4.1Introduction (40)

4.2Design Speci?cations (40)

4.3Analog Component Design (42)

4.4Digital Component Design (50)

TABLE OF CONTENTS(Continued)

Page

4.4.1Clock Generator (52)

4.4.2Finite State Machine (56)

4.5Full Chip Simulation (57)

Chapter5:Summary and Future Work61 5.1Summary (61)

5.2Plan of Future Work (62)

Bibliography63

LIST OF FIGURES

Figure Page

2.1General successive approximation ADC (6)

2.2Circuit of16-bit switched-capacitor SAR-A/D converter (9)

2.3Circuits of switch setting1through switch setting4 (10)

2.4Circuits of switch setting5through switch setting8 (11)

2.5Circuits of switch setting9through switch setting12 (12)

2.6Circuits of switch setting13and switch setting14 (13)

2.7Mismatch error cancellation for ADD/ADD operation (14)

3.1Demonstration of input signal sampling (25)

3.2Demonstration of normal converting cycles (27)

3.3Harmonic distortion caused by op-amp non-ideality still exists after

normal CDS (31)

3.4predictive CTS operation (35)

3.5Output spectrum of a SAR–ADC with predictive CDS,op-amp

,no mismatch and parasitic (36)

3.6Output spectrum of a SAR–ADC with predictive CTS,op-amp

,no mismatch and parasitic (37)

3.7Output spectrum of a SAR–ADC with predictive CDS.op-amp

,mismatch and parasitic exist (37)

3.8Output spectrum of a SAR–ADC with predictive CTS.op-amp

,mismatch and parasitic exist (38)

4.1Modi?cation of circuit from normal predictive CDS to double pre-

dictive CDS (42)

4.2Implementation of the comparator (43)

4.3Two stage class A/AB operational ampli?er (44)

4.4Bias circuit of the operational ampli?er (44)

LIST OF FIGURES(Continued)

Figure Page

4.5Switched capacitor common mode feedback circuit (44)

4.6Typical frequency response of the two stage class A/AB operational

ampli?er (46)

4.7Pre-ampli?er of comparator (47)

4.8Bias circuit of the pre-ampli?er of comparator (47)

4.9Comparator latch (48)

4.10NMOS switch-on resistance varies with switch size (49)

4.11CMOS switch-on resistance with different switch sizes vary with

settling voltage (49)

4.12CMOS switch-on transconductances and (51)

4.13CMOS switch-on transconductance (51)

4.14Top level of digital block relative to analog block of the SC SAR–ADC52

4.15Timing diagram of the clock generator (53)

4.16Circuit implementation of clock generator (55)

4.17State transition diagram of SAR–ADC (56)

4.18Circuit implementation of state machine (58)

4.19Output spectrum of the switched capacitor SAR–ADC by full chip

simulation (59)

4.20Layout of the switched-capacitor successive approximation ADC..60

LIST OF TABLES

Table Page

2.1ADD/ADD Sequence (17)

2.2ADD/SUB Sequence (18)

2.3SUB/ADD Sequence (19)

2.4SUB/SUB Sequence (20)

4.1Switched Capacitor SAR ADC Speci?cations (41)

ERROR CANCELING LOW VOLTAGE SAR-ADC

Chapter1

Introduction

1.1Motivation

Signal processing is one of the major incentives to the fast development of electronic circuits.With the tremendous advancement of modern VLSI technology,people are able to build more and more complex digital circuits on a single chip to realize signal processing that is conventionally achieved by analog circuits,because digital circuit has advantages over its analog counterpart in several aspects such as much lower noise sensitivity,excellent signal regenerating capability.and it is easier to realize design and test automation as well.However,the object of signal processing-phys-ical signals of the real world are always in analog form.Therefore,to facilitate the extensive DSP functions in the digital domain,interfaces between analog and digi-tal blocks are omnipresent in all modern mixed signal processing integrated circuits. Analog to digital data converters are among the major components in the interfaces.

There are three conceptually distinct operations that are performed sequentially by an A/D converter[17]:(1)It samples a continuous-valued,continuous-time ana-log signal;(2)it quantizes the sampled signal to a?nite number of levels;(3)it assign a digital code to the related quantized level.With this sequence of operations,any physical signal,no matter if it is mechanical,thermal,optical,acoustical,or magnet-ical,once it has been transformed into electrical signal by a proper sensor,it can be

2 converted into digital signal by an A/D converter and processed conveniently with powerful digital signal processing components,out of which various useful informa-tion can be extracted.

There are many approaches to realizing the analog-to-digital conversion.Some of these techniques,such as?ash and pipeline[10]A/D converters trade off accuracy for speed.On the other end of the scale the highest accuracy is realized by oversampling A/D converters[13,15],which have high tolerance to technological imperfections and component parameter variations but low conversion speed and high power con-sumption.The compromise between conversion speed and accuracy is achieved by Nyquist rate A/D converters such as algorithmic[9,11]and successive approximate A/D converters,which have moderate speed and moderate precision.

Switched capacitor circuits have become popular because of their good linear-ity and dynamic range.Naturally,switched capacitor techniques are also applied to Nyquist rate A/D converters.However,if the conversions are realized by simple charge transfer between ratio-matched capacitors,as it did in the work of McCha-rles,et al.[11]as an early algorithmic A/D converter,the conversion accuracy will be fundamentally limited by the ratio accuracy.To overcome this problem,several circuit con?gurations have been proposed which perform the cyclic conversion in a capacitor ratio independent manner[8,9,20,23].In those approaches the conver-sion speed was sacri?ced for ratio-independent property substantially.For instance, 6clock cycles were needed for each bit’s conversion in the design of Li,et al.[9] compared to2clocks in[11].The approach proposed by Onodera,et al.[14]was able to decrease the number of clocks down to3for each bit.A further improve-ment for conversion speed without losing the ratio-independent feature was realized by Zheng,et al.[26],where a fully differential circuit structure was used and only2 clocks were needed for each bit’s conversion,which has the same conversion speed

3 as that of the ratio-dependent structure proposed by McCharles,et al.[11].

Similar to switched-capacitor algorithmic ADC,another type of Nyquist rate ADC–switched-capacitor successive approximation ADC also suffers from capac-itor mismatch errors.Apart from developing a ratio-independent circuit structure, mismatch-shaping techniques([1,3,19])can be used to decrease the error.The ap-proach proposed by Rombouts,et al.[18]realized the?rst order error cancellation, where a nearly distortion-free converter is obtained by employing additional signal processing with the cost of two fold increase of conversion time.To further improve the switched capacitor successive approximation ADC,a novel mismatch error can-celing algorithm was proposed by Zheng,et al.[27],where only50%of conversion time is needed to eliminate the?rst order mismatch error.As the continuation of this research,this thesis aims to improve the proposed algorithm and realize the cir-cuit on a chip,which will be the test vehicle for the proposed circuitry for further improvement.

1.2Thesis Structure

Chapter2describes the principle of successive approximate A/D converters,and gen-eral considerations of circuit non-ideality in realizing a switched capacitor successive A/D converter.Based on the detailed charge domain analysis of the ADC operations, an improvement of the algorithm proposed by Zheng,et al.[27]is provided by trac-ing the error charge free capacitor.To summarize the complete algorithm,4tables

4 representing the detailed operational sequences of the ADC to be designed are pro-vided at the end of this chapter.

Chapter3studies the characteristics of the predictive correlated double sampling technique in switched capacitor successive approximation ADC.A detailed theoret-ical analyze of the operations of the proposed SC SAR–ADC is given.MATLAB simulations based on the theoretical results show that the conventional predictive CDS is not adequate to achieve high resolution SC SAR–ADC.The subtle difference in signal processing manners between predictive CDS in SC SAR-ADC and other ap-plications is discussed.Further more,the predictive correlated triple sampling(CTS) technique is proposed to improve the inadequacy of predictive CDS in SAR–ADC, and this improvement is veri?ed by SWITCAP simulations.

Chapter4gives the detailed design of the proposed SC SAR–ADC with National Semiconductor low voltage technology.Transistor level full chip simulation is given at the end of this chapter.

Chapter5summarizes the work of this thesis and the plan of future work.

5

Chapter2

Mismatch Error Cancellation Algorithm

2.1Conceptual Operation of a Successive Approximation ADC

Because of its reasonably high conversion speed with moderate circuit complexity and converting accuracy,successive approximation A/D converters(SAR–ADCs) are among those of the most popular Nyquist rate ADCs.The terms“Divided Refer-ence Algorithm”or“Binary Search Algorithm”can be used to best describe the basic principle of a SAR–ADC.

Figure2.1depicts a possible scenario of the operation for a SAR–ADC to an input signal,which is sampled at the beginning of each conversion cycle.Con-version starts with the comparison between input signal and the half reference voltage,which determines the MSB of and also determines the search region for the second MSB.In order to allow the binary search algorithm to approximate the actual,the reference voltage used for MSB will be divided by2and the result will be added to or subtracted from the previous reference voltage,which delimitates the new binary search regions.As such,each comparison between and updated reference voltage generates one bit of,and N bits SAR-ADC will need N com-parisons.

6

k

FIGURE2.1:General successive approximation ADC

2.2Circuit Non-idealities

Obviously,the above description is based on the ideal operation of a general SAR ADC.In real circuits,the“divided by two”operation to the reference voltage can be realized in various ways.In case of a switched capacitor circuit,it is normally implemented by sharing reference charge with two matched capacitors,as described in the paper by Zheng et al.[27].Therefore any mismatch error between the two capacitors used to share charge will have a direct impact on the linearity of the overall converter.

Besides the capacitor mismatch error,there are other circuit non-idealities.In the low voltage design context,it is dif?cult to obtain high op-amp gain,thus circuit imperfection caused by op-amp?nite gain is inevitable.Other non-avoidable circuit

7 non idealities include op-amp offset voltage,parasitic capacitances,charge injection and clock feedthrough,etc.The following is a brief description of a novel technique proposed by Zheng[25]to cope with above circuit imperfection.

2.3A Novel Capacitor Mismatch Error Cancellation Technique for Switched

Capacitor SAR–ADC

A novel capacitor mismatch error cancellation technique for switched capacitor SAR –ADC has been proposed by Zheng[25].With this technique,the?rst order ca-pacitor mismatch error is virtually eliminated at the cost of increasing by50%the data conversion time.This is less than that required in a capacitance ratio inde-pendent cyclic A/D converter,where typically100%additional conversion time is needed compared to the ideal operation.With this technique,not only the capaci-tance mismatch error has been cancelled,op-amp?nite gain and offset voltage are also compensated by the application of the correlated double sampling(CDS)tech-nique.Through the proper path arrangement of charge transfer in a fully differential structure,the in?uence of top plate parasitic capacitances are also suppressed.

Since there are16capacitors in the ADC core,in order to describe the operation more clearly,it is convenient to have a method for the systematic identi?cation of each capacitor.The following convention will be used for the identifying subscripts of the capacitors:

First subscript:

i or int—denotes an integrating capacitor;

r or ref—denotes a capacitor which stores a reference charge;

s or sig—denotes a signal capacitor,which shares charge with reference ca-

8 pacitor;

e or err—denotes an error charge capacitor for CDS compensation.

Second subscript:

1—denotes capacitors connected to the inverting input side of the fully differ-ential op-amp;

2—denotes capacitors connected to the non-inverting input side of the fully differential op-amp.

Third subscript:

D or DAC—denotes CDS error charge capacitors of the op-amp;

C or Comp—denotes CDS error charge capacitors of the comparator;

p(predicting)—denotes capacitors used in predicting phase(of CDS opera-tion);

c(converting)—denotes capacitors used in converting phase(of CDS opera-tion).

Then,the16capacitors in the circuit are

9

F I

G U R E 2.2:C i r c u i t o f 16-b i t s w i t c h e d -c a p a c i t o r S A R -A /D c o n v e r t e r

10

The complete circuit diagram of the switched-capacitor SAR A/D converter im-plementing the capacitor mismatch error cancellation algorithm is shown in Fig.2.2.Drawing the connection of the crucial elements switched in each of the 6phases needed to derive two bits in the digital output results in 14different circuit con?gu-rations shown in Fig.2.3through Fig.

2.6.Switch setting 1

(a)Switch setting 2

(b)Switch setting 3

(c)Switch setting 4(d)

FIGURE 2.3:Circuits of switch setting 1through switch setting 4

11Switch setting 5

(a)Switch setting 6

(b)Switch setting 7

(c)Switch setting 8(d)

FIGURE 2.4:Circuits of switch setting 5through switch setting 8

Each conversion starts with the sampling of input signal,which stores the input signal in integrating capacitor by charge of .For purpose of compari-son with reference charge,sampling charge can be stored as its opposite value

conveniently through cross coupling of the differential branches.This sam-pling process is implemented by the two switch con?gurations (switch setting 1and

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