DS4026-MCC中文资料

General Description

The DS4026 is a temperature-compensated crystal oscillator (TCXO) that provides ±1ppm frequency sta-bility over the -40°C to +85°C industrial temperature range. Each device is factory calibrated over tempera-ture to achieve the ±1ppm frequency stability. Standard frequencies for the device include 12.8, 19.44, 20.0,38.88, 40.0, and 51.84MHz. Contact the factory for cus-tom frequencies.

The DS4026 provides excellent phase-noise characteris-tics. The output is a push-pull CMOS square wave with symmetrical rise and fall times. In addition, the DS4026 is designed to provide a maximum frequency deviation of less than ±4.6ppm over 10 years. The device also pro-vides an I 2C interface to allow pushing and pulling of the output frequency by a minimum of ±15ppm typical with typical 1ppb resolution.

The DS4026 implements a temperature-to-voltage con-version with a nonlinear relationship. The output from the temperature-to-voltage converter is used to drive the volt-age-controlled crystal oscillator to compensate for fre-quency change.

The device implements an on-chip temperature sensor lookup table,and a digital-to-analog converter (DAC) to adjust the frequency. An I 2C interface used to communi-cate with the DS4026 performs temperature readings and frequency push-pull.

Applications

Reference Clock Generation Wireless

Telecom/Datacom/SATCOM

Test and Measurement

Features

?±1ppm Frequency Accuracy Over -40°C to +85°C ?Standard Frequencies: 12.8, 19.44, 20.0, 38.88,40.0, 51.84MHz ?Maximum ±4.6ppm Deviation Over 10 Years ?Minimum ±8ppm Digital Frequency Tuning Through I 2C Interface ?Surface-Mount 16-Pin SO Package ?Pb Free/RoHS Compliant

DS4026

12.8MHz to 51.84MHz TCXO

______________________________________________Maxim Integrated Products 1

Rev 0; 2/07

For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.docsj.com/doc/6c16755345.html,.

+Lead-free package.

*The top mark will include a “+” for a lead-free/RoHS-compliant device.

Ordering Information continued at end of data sheet.

Ordering Information

D S 4026

12.8MHz to 51.84MHz TCXO 2_____________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED DC OPERATING CONDITIONS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on V CC , V CCD , and V OSC

Relative to Ground..............................................-0.3V to +3.8V Voltage Range on SDA, SCL, and FOUT

Relative to Ground...................................-0.3V to (V CC + 0.3V)

Operating Temperature Range (noncondensing)....-40°C to +85°C Storage Temperature Range.............................-55°C to +125°C Soldering Temperature………………………….See IPC/JEDEC

J-STD-020 Specification

DC ELECTRICAL CHARACTERISTICS (Note 1)

DS4026

12.8MHz to 51.84MHz TCXO

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AC ELECTRICAL CHARACTERISTICS (Note 1)

D S 4026

12.8MHz to 51.84MHz TCXO 4_____________________________________________________________________

TEMPERATURE SENSOR ELECTRICAL CHARACTERISTICS (Note 1)

AC ELECTRICAL CHARACTERISTICS

DS4026

12.8MHz to 51.84MHz TCXO

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Note 2:Voltages referenced to ground.

Note 3:Limits at -40°C are guaranteed by design and not production tested.Note 4:Specified with I 2C bus inactive.

Note 5:Guaranteed by design and not production tested.Note 6:After this period, the first clock pulse is generated.

Note 7:

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IH(MIN)of the SCL signal)to bridge the undefined region of the falling edge of SCL.

Note 8:The maximum tHD:DAT need only be met if the device does not stretch the low period (t LOW ) of the SCL signal.

Note 9: A fast-mode device can be used in a standard-mode system, but the requirement that t SU:DAT ≥250ns must then be met.

This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does not stretch the low period of the SCL signal, it must output the next data bit to the SDA line t R(MAX)+ t SU:DAT = 1000 + 250 =1250ns before the SCL line is released.

Note 10:C B —total capacitance of one bus line in pF.

AC ELECTRICAL CHARACTERISTICS (continued)

Data Transfer on I 2C Serial Bus

D S 4026

12.8MHz to 51.84MHz TCXO 6_____________________________________________________________________

Typical Operating Characteristics

(V CC = +3.3V, T A = +25°C, unless otherwise noted.)

ACTIVE-SUPPLY CURRENT vs. POWER-SUPPLY CURRENT

V CC (V)

C U R R E N T (m A )

3.53.43.33.2

3.1

0.30.20.10.60.50.40.80.70.91.11.01.41.31.21.61.50

3.0

3.6ACTIVE-SUPPLY CURRENT vs. OSCILLATOR POWER SUPPLY

V OSC (V)

C U R R E N T (m A )

3.53.43.33.23.10.51.01.52.02.53.03.5

4.04.5

5.00

3.0 3.6ACTIVE-SUPPLY CURRENT vs. DRIVER POWER SUPPLY

V CCD (V)

C U R R E N T (m A )

3.53.43.33.23.18.06.0

4.0

2.010.0

-0.1

3.0

3.6

FREQUENCY vs. FTUNE

VC (V)

O F F S E T (p p m )

000h 4000h

-25-20-15-10-505101520

-30

3FFFh FREQUENCY vs. TEMPERATURE

TEMPERATURE (°C)

D E V I A T I O N (p p m )

6040200

-20

-10-13-8-3-531513108518020-15

-40

80

DS4026

12.8MHz to 51.84MHz TCXO

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D S 4026

12.8MHz to 51.84MHz TCXO 8_____________________________________________________________________

Figure 2. Functional Diagram

Detailed Description

The DS4026 is a TCXO capable of operating at 3.3V ±10%, and it allows digital tuning of the fundamental frequency. The device is calibrated in the factory to achieve an accuracy of ±1ppm over the industrial tem-perature range, and its minimum pullability is ±8ppm with a typical resolution of 1ppb (typ) per LSB.The DS4026 contains the following blocks:

?Oscillator block with variable capacitor for compen-sation ?Output driver block ?Temperature sensor

?Controller to read the temperature, control lookup table, and adjust the DAC input

?DAC output to adjust the capacitive load

?I 2C interface to communicate with the chip

The oscillator block consists of an amplifier and variable capacitor in a Pierce crystal oscillator with a crystal res-onator of fundamental mode. The oscillator amplifier is a single transistor amplifier and its transconductance is temperature compensated. The variable capacitor is adjusted by the DAC to provide temperature compen-sation. With the FTUNEH and FTUNEL registers, a mini-mum pullability of ±15ppm (typ) is achieved with a typical resolution of 1ppb (typ) per LSB.

DS4026

The output driver is a CMOS square-wave output with symmetrical rise and fall time.

The temperature sensor provides a 12-bit temperature reading with a resolution of 0.0625°C. The sensor is in continuous conversion mode unless the DCOMP bit in the control register is set to disable temperature updates.The controller coordinates the conversion of tempera-ture into digital codes. When the temperature reading is different from the previous one or the frequency tuning register is changed, the controller looks up the two cor-responding capacitance trim codes from the lookup table at a 0.5°C increment. The trim codes are interpo-lated to 0.0625°C resolution.

The result is added with the tuning value from the fre-quency tuning register and loaded into the DAC regis-ters to adjust voltage output. The monotonic DAC provides an analog voltage based on temperature compensation to drive the variable capacitor.

The DS4026 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code fol-lowed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed.

Address Map

Disable Compensation Update (DCOMP)

DCOMP is bit 7 of the frequency tuning register (see the Frequency Tuning Register (00h–01h), POR = 00h table). When set to logic 1, this bit’s temperature-com-pensation function is disabled. This disabling prevents the variable capacitor in the oscillator block from changing. However, the temperature register still per-forms temperature conversions. The temperature trim code from the last temperature conversion before DCOMP is enabled is used for temperature compensa-tion. The FTUNE registers are still functional when DCOMP is disabled.

The frequency tuning registers adjust the base frequen-cy. The frequency tuning value is represented in two’s complement data. Bit 6 of FTUNEH is the sign, bit 5 is the MSB, and bit 0 of FTUNEL is the LSB (see Table 1).When the tuning register low (01h) is programmed with a value, the next temperature update cycle sums the programmed value with the factory compensated value. This allows the user to digitally control the base frequency using the I 2C protocol.

These frequency tuning register bits allow the tuning of the base frequency. Each bit typically represents about 1ppb (typ). For FTUNEH = 3Fh and FTUNEL =FFh, the device pushes the base frequency by approx-imately +15ppm.

12.8MHz to 51.84MHz TCXO

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D S 4026

In the temperature register (see the Temperature Register (02h–03h)table), temperature is represented as a 12-bit code and is accessible at location 02h and 03h. The upper 8 bits are at location 02h and the lower 4 bits are in the upper nibble of the byte at location 03h. Upon power reset, the registers are set to a +25°C default temperature and the controller starts a tempera-ture conversion. The temperature register stores new temperature readings.

The current temperature is loaded into the (user) tem-perature registers when a valid I 2C slave address and write is received and when a word address is received.Consequently, if the two temperature registers are read in individual I 2C transactions, it is possible for a temper-ature conversion to occur between reads, and the results can be inaccurate. To prevent this from occur-ring, the registers should be read using a single, multi-byte read operation (Figure 5). I 2C reads do not affect the internal temperature registers.

I The DS4026 supports a bidirectional I 2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiv-ing data is defined as a receiver. The device that con-trols the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and gener-ates the START and STOP conditions. The DS4026operates as a slave on the I 2C bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS4026works in both modes.

The following bus protocol has been defined (Figure 3):?Data transfer can be initiated only when the bus is not busy.

12.8MHz to 51.84MHz TCXO 10

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Figure 3. I C Data Transfer Overview

?During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy:Both data and clock lines remain high.Start data transfer:A change in the state of the data line from high to low, while the clock line is high,defines a START condition.

Stop data transfer:A change in the state of the data line from low to high, while the clock line is high,defines a STOP condition.

Data valid:The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge (ACK) after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition.Figures 4 and 5 detail how data transfer is accom-plished on the I 2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible:

Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge (ACK) bit after each received byte.Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is trans-mitted by the master. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge (NACK) is returned.

The master device generates all the serial clock pulses and the START and STOP conditions. A trans-fer is ended with a STOP condition or with a repeat-ed START condition. Because a repeated START condition is also the beginning of the next serial transfer, the bus is not released.

DS4026

12.8MHz to 51.84MHz TCXO

____________________________________________________________________

11

Figure 4. Slave Receiver Mode (Write Mode)

Figure 5. Slave Transmitter Mode (Read Mode)

D S 4026

12.8MHz to 51.84MHz TCXO

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600?2007 Maxim Integrated Products

is a registered trademark of Maxim Integrated Products, Inc.

is a registered trademark of Dallas Semiconductor Corporation.

Package Information

For the latest package outline information, go to

The DS4026 can operate in the following two modes:Slave receiver mode (write mode):Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is transmitted.START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the mas-ter generates a START condition. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W ), which is 0 for a write. After receiving and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. After the DS4026 acknowledges the slave address and write bit, the master transmits a word address to the DS4026. This sets the register pointer on the DS4026, with the DS4026 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS4026 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write.

Slave transmitter mode (read mode):The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indi-cates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS4026 while the serial clock is input on SCL. START and STOP condi-tions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condi-tion. The slave address byte contains the 7-bit DS4026 address, which is 1000001, followed by the direction bit (R/W ), which is 1 for a read. After receiv-ing and decoding the slave address byte, the DS4026 outputs an acknowledge on SDA. The DS4026 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initia-tion of a read mode, the first address that is read is the last one stored in the register pointer. The DS4026 must receive a not acknowledge to end a read.

Chip Information

TRANSISTOR COUNT: 77, 712

SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS

Ordering Information (continued)

+Lead-free package.

*The top mark will include a “+” for a lead-free/RoHS-compliant device.