ATT3064-100J84I中文资料
Data Sheet February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
s High performance:
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
s User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system logic changes
s Flexible array architecture:
— Compatible arrays ranging from 1500 to 6000 gate logic complexity
— Extensive register, combinatorial, and I/O capabilities
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator ampli?er
s Standard product availability:
— Low-power 0.55 μm CMOS, static memory technology
— Pin-for-pin compatible with Xilinx*XC3000* and XC3100* families
— Cost-effective for volume production
— 100% factory pretested
— Selectable con?guration modes
s ORCA? Foundry for ATT3000Development System support
s All FPGAs processed on a QML-certi?ed line s Extensive packaging options Description
The CMOS ATT3000 Series Field-Programmable Gate Array (FPGA) family provides a group of high-density, digital integrated circuits. Their regular, extendable, ?exible, user-programmable array architecture is composed of a con?guration program store plus three types of con?gurable elements: a perimeter of I/O blocks, a core array of logic blocks, and resources for interconnection. The general struc-ture of an FPGA is shown in Figure 1.
The ORCA Foundry for ATT3000 Development Sys-tem provides automatic place and route of netlists. Logic and timing simulation are available as design veri?cation alternatives. The design editor is used for interactive design optimization and to compile the data pattern that represents the con?guration pro-gram.
The FPGA’s user-logic functions and interconnec-tions are determined by the con?guration program data stored in internal static memory cells. The pro-gram can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM, or ROM on the application circuit board, or on a ?oppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of pro-gram data at powerup. A serial con?guration PROM can provide a very simple serial con?guration pro-gram storage.
*Xilinx, XC3000, and XC3100 are registered trademarks of Xilinx, Inc.
Table 1. ATT3000 Series FPGAs
FPGA
Max
Logic
Gates
Typical Gate
Range
Con?gurable
Logic
Blocks
Array
User I/Os
Max
Flip-
Flops
Horizontal
Long Lines
Con?guration
Data Bits
ATT30201,5001,000—1,500648 x 8642561614,779 ATT30302,0001,500—2,00010010 x 10803602022,176 ATT30423,0002,000—3,00014412 x 12964802430,784 ATT30644,5003,500—4,50022416 x 141206883246,064 ATT30906,0005,000—6,00032020 x 161449284064,160
Data Sheet ATT3000 Series Field-Programmable Gate Arrays
February 1997
2Lucent Technologies Inc.
Contents
Page
Performance .............................................................29Device Performance .............................................29Logic Block Performance ......................................30Interconnect Performance .....................................30Power ........................................................................32Power Distribution .................................................32Power Dissipation .................................................33Pin Information .........................................................34Pin Assignments .......................................................39Package Thermal Characteristics .............................50Package Coplanarity .................................................51Package Parasitics ...................................................51Absolute Maximum Ratings ......................................53Electrical Characteristics ..........................................54Outline Diagrams ......................................................68Terms and De?nitions ...........................................6844-Pin PLCC .........................................................6868-Pin PLCC .........................................................6984-Pin PLCC .........................................................70100-Pin QFP .........................................................71100-Pin TQFP .......................................................72132-Pin PPGA ......................................................73144-Pin TQFP .......................................................74160-Pin QFP .........................................................75175-Pin PPGA ......................................................76208-Pin SQFP .......................................................77Ordering Information . (78)
Contents
Page
Features .....................................................................1Description .................................................................1Architecture ................................................................3Con?guration Memory................................................ 4I/O Block .....................................................................5Summary of I/O Options .........................................6Con?gurable Logic Block ............................................7Programmable Interconnect .......................................9General-Purpose Interconnect .............................10Direct Interconnect ...............................................11Long Lines ............................................................13Internal Buses ......................................................14Crystal Oscillator ..................................................16Con?guration ............................................................17Initialization Phase ...............................................17Con?guration Data ...............................................19Con?guration Modes ................................................22Master Mode ........................................................22Peripheral Mode ...................................................24Slave Mode ..........................................................25Daisy Chain ..........................................................26Special Con?guration Functions ..............................27Input Thresholds ...................................................27Readback .............................................................27Reprogram ...........................................................28DONE Pull-Up ......................................................28DONE Timing .......................................................28RESET Timing ......................................................28Crystal Oscillator Division (28)
Table of Contents
Data Sheet February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
3
Architecture
The perimeter of con?gurable I/O blocks (IOBs) pro-vides a programmable interface between the internal logic array and the device package pins. The array of con?gurable logic blocks (CLBs) performs user-speci?ed logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed-circuit board traces connecting MSI/SSI packages.The blocks’ logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers.Interconnecting networks between blocks are
implemented with metal segments joined by program-controlled pass transistors. These functions of the FPGA are established by a con?guration program which is loaded into an internal, distributed array of con?guration memory cells. The con?guration program is loaded into the FPGA at powerup and may be
reloaded on command. The FPGA includes logic and control signals to implement automatic or passive con?guration. Program data may be either bit serial or byte parallel. The ORCA Foundry for ATT3000 Devel-opment System generates the con?guration program bit stream used to con?gure the FPGA. The memory loading process is independent of the user logic func-tions.
Figure 1. Field-Programmable Gate Array Structure
Data Sheet ATT3000 Series Field-Programmable Gate Arrays
February 1997
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Con?guration Memory
The static memory cell used for the con?guration mem-ory in the FPGA has been designed speci?cally for high reliability and noise immunity. Integrity of the FPGA con?guration memory based on this design is ensured even under various adverse conditions. Com-pared with other programming alternatives, static mem-ory is believed to provide the best combination of high density, high performance, high reliability, and compre-hensive testability.
As shown in Figure 2, the basic memory cell consists of two CMOS inverters plus a pass transistor used for writing and reading cell data. The cell is only written to during con?guration and only read from during read-back. During normal operation, the cell provides contin-uous control and the pass transistor is off and does not affect cell stability. This is quite different from the opera-tion of conventional memory devices, in which the cells are frequently read and rewritten.
The memory cell outputs Q and Q use full ground and V CC levels and provide continuous, direct control. The additional capacitive load and the absence of address decoding and sense ampli?ers provide high stability to the cell. Due to their structure, the con?guration mem-ory cells are not affected by extreme power supply excursions or very high levels of alpha particle radia-tion. Soft errors have not been observed in reliability testing.
Two methods of loading con?guration data use serial data, while three use byte-wide data. The internal con-?guration logic utilizes framing information, embedded in the program data by the ORCA Foundry Develop-ment System, to direct memory cell loading. The serial data framing and length count preamble provide pro-gramming compatibility for mixes of various Lucent pro-grammable gate arrays in a synchronous, serial, daisy-chain fashion.
Figure 2. Static Con?guration Memory Cell
CONFIGURATION CONTROL 5-3101(F)
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I/O Block (continued)
For reliable operation, inputs should have transition times of less than 100 ns and should not be left ?oat-ing. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This can produce additional power dissipation and system noise. A
typical hysteresis of about 300 mV reduces sensitivity to input noise. Each user IOB includes a programmable high-impedance pull-up resistor which is selected by the program to provide a constant high for otherwise undriven package pins. Normal CMOS handling precautions should be observed.
Flip-?op loop delays for the IOB and logic block ?ip-?ops are approximately 3 ns. This short delay provides good performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a metastable condition which can result from asser-tion of the clock during data transitions. Because of the short loop delay characteristic in the FPGA, the IOB ?ip-?ops can be used to synchronize external signals applied to the device. When synchronized in the IOB, the signals can be used internally without further con-sideration of their clock relative timing, except as it applies to the internal logic and routing path delays. Output buffers of the IOBs provide CMOS-compatible 4 mA source-or-sink drive for high fan-out CMOS or TTL compatible signal levels. The network driving IOB pin .o becomes the registered or direct data source for the output buffer. The 3-state control signal (IOB pin .t) can control output activity. An open-drain type output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer out-put is enabled only for a LOW.
Con?guration program bits for each IOB control
features such as optional output register, logical signal inversion, and 3-state and slew rate control of the out-put.
The program-controlled memory cells in Figure 3 control the following options:
s
Logical inversion of the output is controlled by one con?guration program bit per IOB.
s
Logical 3-state control of each IOB output buffer is determined by the states of con?guration program bits which turn the buffer on or off or select the output buffer 3-state control interconnection (IOB pin .t). When this IOB output control signal is high, a logic 1, the buffer is disabled and the package pin is high impedance. When this IOB output control signal is low, a logic 0, the buffer is enabled and the package pin is active. Inversion of the buffer 3-state control logic sense (output enable) is controlled by an addi-tional con?guration program bit.
s
Direct or registered output is selectable for each IOB. The register uses a positive-edge, clocked ?ip-?op. The clock source may be supplied (IOB pin .ok) by either of two metal lines available along each die edge. Each of these lines is driven by an invertible buffer.
s
Increased output transition speed can be selected to improve critical timing. Slower transitions reduce capacitive load peak currents of noncritical outputs and minimize system noise.
s
A high-impedance pull-up resistor may be used to prevent unused inputs from ?oating.
Summary of I/O Options
s
Inputs —Direct
—Flip-?op/latch
—CMOS/TTL threshold (chip inputs)—Pull-up resistor/open circuit s
Outputs
—Direct/registered —Inverted/not —3-state/on/off
—Full speed/slew limited
—3-state/output enable (inverse)
Data Sheet February 1997
ATT3000 Series Field-Programmable Gate Arrays
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Data Sheet ATT3000 Series Field-Programmable Gate Arrays February 1997
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Data Sheet February 1997
ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect
Programmable interconnection resources in the FPGA provide routing paths to connect inputs and outputs of the IOBs and logic blocks into logical networks. Inter-connections between blocks are composed from a two-layer grid of metal segments. Specially designed pass transistors, each controlled by a con?guration bit, form programmable interconnect points (PIPs) and switching matrices used to implement the necessary connections between selected metal segments and block pins.Figure 7 is an example of a routed net. The ORCA Foundry Development System provides automatic rout-ing of these interconnections. Interactive routing is also available for design optimization. The inputs of the logic or IOBs are multiplexers which can be programmed to select an input network from the adjacent interconnect segments. Since the switch connections to block inputs are unidirectional (as are block outputs), they are
usable only for block input connection and not routing. Figure 8 illustrates routing access to logic block input variables, control inputs, and block outputs.
Three types of metal resources are provided to accom-modate various network interconnect requirements:
s General-purpose interconnect s Direct connection
s
Long lines (multiplexed buses and wide-AND gates)
Figure 7. Example of Routing Resources
Figure 8. CLB Input and Output Routing
Data Sheet ATT3000 Series Field-Programmable Gate Arrays
February 1997
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Figure 9. FPGA General-Purpose Interconnect
Figure 10. Switch Matrix Interconnection Options
12345
678910
1112131415
1617181920
Data Sheet
February 1997ATT3000 Series Field-Programmable Gate Arrays
Programmable Interconnect (continued) Array Direct Interconnect
Direct interconnect (shown in Figure 11) provides the
most ef?cient implementation of networks between
adjacent logic or IOBs. Signals routed from block to
block using the direct interconnect exhibit minimum
interconnect propagation and use no general intercon-
nect resources. For each CLB, the .x output may be
connected directly to the .b input of the CLB immedi-
ately to its right and to the .c input of the CLB to its left.
The .y output can use direct interconnect to drive the .d
input of the block immediately above, and the .a input
of the block below. Direct interconnect should be used
to maximize the speed of high-performance portions of
logic. Where logic blocks are adjacent to IOBs, direct
connect is provided alternately to the IOB inputs (.i)
and outputs (.o) on all four edges of the die. The right
edge provides additional direct connects from CLB out-
puts to adjacent IOBs. Direct interconnections of IOBs
with CLBs are shown in Figure 12.
Figure 11. Direct Interconnect
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Programmable Interconnect
(continued)
Figure 12. ATT3020 Die Edge I/O Blocks with Direct Access to Adjacent CLB
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Programmable Interconnect (continued)
Long Lines
The long lines bypass the switch matrices and are intended primarily for signals which must travel a long distance, or must have minimum skew among multiple destinations. Long lines, shown in Figure 13, run vertically and horizontally the height or width of the interconnect area. Each interconnection column has three vertical long lines, and each interconnection row has two horizontal long lines. Additionally, two long
lines are located adjacent to the outer sets of switching matrices. Two vertical long lines in each column are connectable half-length lines, except on the ATT3020, where only the outer long lines serve that function. Long lines can be driven by a logic block or IOB output on a column-by-column basis. This capability provides a common low-skew control or clock line within each column of logic blocks. Interconnections of these long lines are shown in Figure 14. Isolation buffers are pro-vided at each input to a long line and are enabled auto-matically by the development system when a connection is made.
Figure 13. Horizontal and Vertical Long Lines in the FPGA
3-
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Programmable Interconnect (continued)
A buffer in the upper left corner of the FPGA chip drives a global net which is available to all .k inputs of logic blocks. Using the global buffer for a clock signal pro-vides a skew-free, high fan-out, synchronized clock for use at any or all of the I/O and logic blocks. Con?gura-tion bits for the .k input to each logic block can select this global line, or another routing resource, as the clock source for its ?ip-?ops. This net may also be pro-grammed to drive the die edge clock lines for IO
B use. An enhanced speed, CMOS threshold, offers direct access to this buffer and is available at the second pad from the top of the left die edge.
A buffer in the lower right corner of the array drives a horizontal long line that can drive programmed connec-tions to a vertical long line in each interconnection column. This alternate buffer also has low skew and high fan-out. The network formed by this alternate buf-fer’s long lines can be selected to drive the .k inputs of the logic blocks. CMOS threshold, high-speed access to this buffer is available from the third pad from the bottom of the right die edge.
Internal Buses
A pair of 3-state buffers is located adjacent to each CLB. These buffers allow logic to drive the horizontal long lines. Logical operation of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long line bus by applying a low logic level on its 3-state control line (see Figure 15A). The user is required to avoid contention that can result from multiple drivers with opposing logic levels. Control of the 3-state input by the same signal that drives the buffer input creates an open-drain wired-AND function. A logical high on both buffer inputs creates a high impedance which represents no contention. A logical low enables the buffer to drive the long line low (see Figure 15B). Pull-up resistors are available at each end of the long line to provide a high output when all con-nected buffers are nonconducting. This forms fast, wide gating functions. When data drives the inputs and sep-arate signals drive the 3-state control lines, these buff-ers form multiplexers (3-state buses). In this case, care must be used to prevent contention through multiple active buffers of con?icting levels on a common line. Figure 16 shows 3-state buffers, long lines, and pull-up resistors.
Figure 14. Programmable Interconnection of Long Lines
3-STATE
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Data Sheet ATT3000 Series Field-Programmable Gate Arrays
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Programmable Interconnect (continued)
Crystal Oscillator
Figure 16 shows the location of an internal high-speed inverting ampli?er which may be used to implement an on-chip crystal oscillator. It is associated with the auxil-iary buffer in the lower right corner of the die. When the oscillator is con?gured and connected as a signal source, two special user IOBs are also con?gured to connect the oscillator ampli?er with external crystal oscillator components as shown in Figure 17. A divide-by-two option is available to ensure symmetry. The oscillator circuit becomes active before con?guration is complete in order to allow the oscillator to stabilize. Actual internal connection is delayed until completion of con?guration. In Figure 17, the feedback resistor, R1, between output and input biases the ampli?er at threshold. The value should be as large as is practical
to minimize loading of the crystal. The inversion of the ampli?er, together with the R-C networks and an AT cut series resonant crystal, produces the 360° phase shift of the Pierce oscillator. A series resistor, R2, may be included to add to the ampli?er output impedance when needed for phase shift control or crystal resistance matching, or to limit the ampli?er input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the ratio of C2/C1. The ampli?er is designed to be used from 1 MHz to one-half the speci-?ed CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with respect to a series resistance. Crystal oscillators above 20 MHz generally require a crystal which operates in a third overtone mode, where the fundamental frequency must be suppressed by an inductor across C2. When the oscillator inverter is not used, these IOBs and their package pins are available for general user I/O.
Suggested component values:
R1—0.5 M ? to 1 M ?
R2—0 k ? to 1 k ? (may be required for low frequency, phase shift, and/or compensation level for Crystal Q)C1, C2—10 pF to 40 pF
Y1—1 MHz to 20 MHz AT cut series resonant Figure 17. Crystal Oscillator Inverter
Pin
44-Pin PLCC 68-Pin PLCC 84-Pin PLCC 100-Pin 132-Pin PPGA 144-Pin TQFP 160-Pin QFP 175-Pin PPGA 208-Pin SQFP QFP TQFP XTAL1 (OUT)3047578279P137582T14110XTAL2 (IN)
26
43
53
76
73
M13
69
76
P15
100
Data Sheet
February 1997ATT3000 Series Field-Programmable Gate Arrays
Con?guration
Initialization Phase
An internal power-on-reset circuit is triggered when power is applied. When V CC reaches the voltage where portions of the FPGA begin to operate (2.5 V to 3 V), the programmable I/O output buffers are disabled and a high-impedance pull-up resistor is provided for the user I/O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time, the power-down mode is inhibited. The initialization state time-out (about 11 ms to 33 ms) is determined by a 14-bit counter driven by a self-generated, internal timer. This nominal 1 MHz timer is subject to variations with pro-cess, temperature, and power supply over the range of 0.5 MHz to 1.5 MHz. As shown in Table 2, ?ve con?gu-ration mode choices are available, as determined by the input levels of three mode pins: M0, M1, and M2.In master con?guration mode, the FPGA becomes the source of con?guration clock (CCLK). Beginning con-?guration of devices using peripheral or slave modes must be delayed long enough for their initialization to be completed. An FPGA with mode lines selecting a master con?guration mode extends its initialization state using four times the delay (43 ms to 130 ms) to ensure that all daisy-chained slave devices it may be driving will be ready, even if the master is very fast and the slave(s), very slow (see Figure 18). At the end of initialization, the FPGA enters the clear state where it clears con?guration memory. The active-low, open-drain initialization signal INIT indicates when the initial-ization and clear states are complete. The FPGA tests for the absence of an external active-low RESET before it makes a ?nal sample of the mode lines and enters the con?guration state. An external wired-AND of one or more INIT pins can be used to control con?guration by the assertion of the active-low RESET of a master mode device or to signal a processor that the FPGAs are not yet initialized.
If a con?guration has begun, a reassertion of RESET for a minimum of three internal timer cycles will be recog-nized and the FPGA will initiate an abort, returning to the clear state to clear the partially loaded con?gura-tion memory words. The FPGA will then resample RESET and the mode lines before reentering the con-?guration state.
A reprogram is initiated when a con?gured FPGA senses a high-to-low transition on the DONE/PROG package pin. The FPGA returns to the clear state where con?guration memory is cleared and mode lines resampled, as for an aborted con?guration. The com-plete con?guration program is cleared and loaded dur-ing each con?guration program cycle.
Table 2. Con?guration Modes
M0M1M2Clock Mode Data
000Active Master Bit Serial
001Active Master Byte Wide
(Address = 0000
up)
010—Reserved—
011Active Master Byte Wide
(Address = FFFF
down)
100—Reserved—
101Active Peripheral Byte Wide
110—Reserved—
111Passive Slave Bit Serial
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Data Sheet ATT3000 Series Field-Programmable Gate Arrays
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Length count control allows a system of multiple FPGAs in assorted sizes to begin operation in a syn-chronized fashion. The con?guration program gener-ated by the ORCA Foundry Development System begins with a preamble of 111111110010 (binary), fol-lowed by a 24-bit length count representing the total number of con?guration clocks needed to complete loading of the con?guration program(s). The data fram-ing is shown in Figure 19. All FPGAs connected in series read and shift preamble and length count in (on positive) and out (on negative) CCLK edges. An FPGA which has received the preamble and length count then presents a HIGH data out until it has intercepted the appropriate number of data frames. When the con?gu-ration program memory of an FPGA is full and the length count does not compare, the FPGA shifts any additional data through, as it did for preamble and length count.
When the FPGA con?guration memory is full and the length count compares, the FPGA will execute a syn-chronous start-up sequence and become operational (see Figure 20 on page 20). Two CCLK cycles after the completion of loading con?guration data, the user I/O pins are enabled as con?gured. As selected in ORCA Foundry, the internal user-logic reset is released either one clock cycle before or after the I/O pins
become active. A similar timing selection is program-mable for the DONE/PROG output signal. DONE/PROG may also be programmed to be an open drain or include a pull-up resistor to accommodate wired-ANDing. The high during con?guration (HDC) and low during con?guration (LDC ) are two user I/O pins which are driven active when an FPGA is in initialization, clear, or con?gure states. These signals and DONE/PROG provide for control of external logic signals such as reset, bus enable, or PROM enable during con?guration.
For parallel master con?guration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or CMOS compatible thresholds. At powerup, all inputs have TTL thresholds and can change to CMOS thresh-olds at the completion of con?guration, if the user has selected CMOS thresholds. The threshold of PWRDWN and the direct clock inputs are ?xed at a CMOS level.If the crystal oscillator is used, it will begin operation before con?guration is complete to allow time for stabilization before it is connected to the internal circuitry.
Data Sheet
February 1997ATT3000 Series Field-Programmable Gate Arrays Array
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Data Sheet ATT3000 Series Field-Programmable Gate Arrays February 1997
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