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DATA BRIEFING
June 2002
Complete data available on Data-on-Disc CD-ROM or at https://www.docsj.com/doc/1012244017.html, .
μPSD3200FAMILY
Flash Programmable System Device
with 8032Microcontroller Core
FEATURES SUMMARY
s The μPSD3200Family combines a Flash PSD architecture with an 8032microcontroller core The μPSD3200Family of Flash PSDs features dual banks of Flash memory,SRAM,general purpose I/O and programmable logic,supervi-sory functions and access via USB,I 2C,ADC,DDC and PWM channels,and an on-board 8032microcontroller core,with two UARTs,three 16-bit Timer/Counters and one External Interrupt.As with other Flash PSD families,the μPSD3200Family is also in-system program-mable (ISP)via a JTAG ISP interface.s
Large 8KByte SRAM with battery back-up option
s
Dual bank Flash memories
–128KByte or 256KByte main Flash memory –32KByte secondary Flash memory
s
Content Security
–Block access to Flash memory
s
Programmable Decode PLD for flexible address mapping of all memories.
s High-speed clock standard 8032core (12-cycle)s USB Interface (μPSD3234A-40U6only)s I 2C interface for peripheral connections s Five Pulse Width Modulator (PWM)channels s Standalone Display Data Channel (DDC)s Six I/O ports with up to 50I/O pins s 3000gate PLD with 16macrocells s Supervisor functions
s In-System Programming (ISP)via JTAG s Zero-Power Technology s
Single Supply Voltage –4.5to 5.5V –3.0to 3.6V
Figure 1.Packages
TQFP52(T)
TQFP80(U)
μPSD3200FAMILY
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SUMMARY DESCRIPTION s Dual bank Flash memories
–Concurrent operation,read from memory one while erasing and writing the other.In-Appli-cation Programming (IAP)for remote updates –Large 128KByte or 256KByte main Flash memory for application code,operating sys-tems,or bit maps for graphic user interfaces –Large 32KByte secondary Flash memory di-vided in small sectors.Eliminate external EE-PROM with software EEPROM emulation –Secondary Flash memory is large enough for sophisticated communication protocol (USB)during IAP while continuing critical system tasks
s
Large SRAM with battery back-up option –8KByte SRAM for RTOS,high-level languag-es,communication buffers,and stacks
s
Programmable Decode PLD for flexible address mapping of all memories
–Place individual Flash and SRAM sectors on any address boundary –Built-in page register breaks restrictive 8032limit of 64KByte address space –Special register swaps Flash memory seg-ments between 8032“program”space and “data”space for efficient In-Application Pro-gramming
s
High-speed clock standard 8032core (12-cycle)–40MHz operation at 5V,24MHz at 3.3V –Two UARTs with independent baud rate,three 16-bit Timer/Counters and two External Interrupts
s
USB Interface (μPSD3234A-40U6only)–Supports USB 1.1Slow Mode (1.5Mbit/s)–Control endpoint 0and interrupt endpoints 1and 2
s
I 2C interface for peripheral connections –Capable of master or slave operation s
Five Pulse Width Modulator (PWM)channels –Four 8-bit PWM units
–One 16-bit PWM unit
s
Standalone Display Data Channel (DDC)–For use in monitor,projector,and TV applica-tions –Compliant with VESA standards DDC1and DDC2B –Eliminate external DDC PROM s Six I/O ports with up to 50I/O pins
–Multifunction I/O:GPIO,DDC,I 2C,PWM,PLD I/O,supervisor,and JTAG –Eliminates need for external latches and logic
s
3000gate PLD with 16macrocells
–Create glue logic,state machines,delays,etc.–Eliminate external PALs,PLDs,and 74HCxx –Simple PSDsoft Express software ...Free
s
Supervisor functions
–Generates reset upon low voltage or watch-dog time-out.Eliminate external supervisor device –Reset In pin
s
In-System Programming (ISP)via JTAG –Program entire chip in 10-25seconds with no involvement of 8032–Allows efficient manufacturing,easy product testing,and Just-In-Time inventory –Eliminate sockets and pre-programmed parts –Program with FlashLINK TM cable and any PC
s
Content Security
–Programmable Security Bit blocks access of device programmers and readers
s
Zero-Power Technology
–Memories and PLD automatically reach standby current between input changes
s
Packages –52-pin TQFP
–80-pin TQFP:allows access to 8032address/data/control signals for connecting to external peripherals
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μPSD3200FAMILY
Figure 2.μPSD3200Family Functional Modules
AI06619
4Channel ADC
1Mb or 2Mb Main Flash
Decode PLD
64Kb SRAM
CPLD -16MACROCELLS
JTAG ISP Port 1Port 32UARTS Interrupt
3Timer /Counters
256Byte SRAM
8051Core Port 3,UART,Intr,Timers,I2C
PSD Internal Bus
8032Internal Bus
USB &
Transceiver
Port 1,Timers and 2nd UART and ADC
DDC w/256Byte SRAM PWM 5Channels Port 4PWM and DDC
Dedicated USB Pins
Port A &B,PLD I/O and GPIO
Port D GPIO Port C,
JTAG,PLD I/O and GPIO
VCC,GND,XTAL
256Kb Secondary Flash
Dedicated Pins
I2C
Port 0,2Ext.Bus
Reset Logic
LVD &WDT
Bus Interface
Reset
D0-D7
A0-A15RD,PSEN WR,ALE
Page Register PSD MODULE
MCU MODULE
μPSD3200FAMILY
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Table 1.80-Pin Package Pin Description
Note:PSD Port A and MCU Address/Data bus are added for 80-pin device
Signal Name In/Out Function
Basic
Alternate
AD7-AD0I/O Multiplexed Address/Data bus A11-A8I/O External Address Bus
RxD2-RxD1I/O General I/O port pins
UART Receive TxD2-TxD1I/O UART Transmit
INT1-INT0I/O Interrupt inputs /timer gate controls T2-T0I/O Counter inputs
SDA1-SDA2I/O
I 2C Bus serial data I/O /DDC interface SCL1-SCL2I/O I 2C Bus clock I/O
VSYNC I/O VSYNC input for DDC interface T2EX I/O Timer 2Trigger input ADC3-ADC0I/O ADC Channels input
PWM4-PWM0I/O 8-bit Pulse Width Modulation outputs
USB-,USB+I/O USB I/O
AVREF O Reference Voltage input for ADC RD_O Read signal,external bus WR_O Write signal,external bus PSEN_O PSEN signal,external bus ALE O Address Latch signal,external bus RESET_I Active low reset input
XTAL1I Oscillator input pin for system clock XTAL2
O
Oscillator output pin for system clock
PA7-P A0I/O General I/O port pins
1.PLD Macro-cell outputs
2.PLD inputs
https://www.docsj.com/doc/1012244017.html,tched Address Out (A0-A7)
4.
Peripheral I/O mode PB7-PB0I/O General I/O port pins
1.PLD Macro-cell outputs
2.PLD inputs
https://www.docsj.com/doc/1012244017.html,tched Address Out (A0-A7)
PC7-PC0I/O General I/O port pins
1.PLD Macro-cell outputs
2.PLD inputs
3.SRAM stand by voltage input (VSTBY)
4.JTAG Interface (TDI,TDO,TMS,TCK,TSTA T,TERR)
5.SRAM battery-on indicator (PC4)PD2-PD1I/O General I/O port pin
1.PLD I/O
2.Clock input to PLD and APD
3.Chip select to PSD Module
μPSD3200FAMILY Figure3.TQFP52Connections
Note:NC=Not Connected
PU=Pull-up resistor required(2k?for3V devices,7.5k?for5V devices)39P1.5/ADC1 38P1.4/ADC0 37P1.3/TXD1 36P1.2/RXD1 35P1.1/T2X 34P1.0/T2
33V CC
32XTAL2
31XTAL1
30P3.7/SCL1 29P3.6/SDA1 28P3.5/T1
27P3.4/T0
PD1 PC7 PC6 PC5 PU PC4 NC V CC GND PC3 PC2 PC1 PC0 1
2
3
4
5
6
7
8
9
10
11
12
13
5
2
5
1
5
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
P
B
P
B
1
P
B
2
P
B
3
P
B
4
P
B
5
V
R
E
F
G
N
D
R
S
T
-
I
N
P
B
6
P
B
7
A
D
C
3
A
D
C
2
1
4
1
5
1
6
1
7
1
8
1
9
2
2
1
2
2
2
3
2
4
2
5
2
6
P
4
.
7
/
P
W
M
4
P
4
.
6
/
P
W
M
3
P
4
.
5
/
P
W
M
2
P
4
.
4
/
P
W
M
1
P
4
.
3
/
P
W
M
G
N
D
P
4
.
2
/
D
D
C
V
S
Y
N
C
P
4
.
1
/
D
D
C
S
C
L
P
4
.
/
D
D
C
S
D
A
P
3
.
/
R
X
D
P
3
.
1
/
T
X
D
P
3
.
2
/
E
X
I
N
T
P
3
.
3
/
E
X
I
N
T
1
AI05790B
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μPSD3200FAMILY
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Figure 4.TQFP80Connections
Note: 1.NC =Not Connected
https://www.docsj.com/doc/1012244017.html,B-needs a pull-up resistor (see the description of the USB function)
60P1.5/ADC1 59P1.4/ADC0 58P1.3/TXD1 57P2.3,A11 56P1.2/RXD1 55P2.2,A10 54P1.1/T2X 53P2.1,A9 52P1.0/T2 51P2.0,A8 50V CC 49XTAL2 48XTAL1 47P0.7,AD7 46P3.7/SCL1 45P0.6,AD6 44P3.6/SDA1 43P0.5,AD5 42P3.5/T1 41P0.4,AD4
PD2 P3.3/EXINT1 PD1 PD0,ALE PC7 PC6 PC5 USB- PC4 USB+ NC V CC GND PC3 PC2 PC1 NC P4.7/PWM4 P4.6/PWM3 PC01
2
3 4
5 6 7 8 9 10 11 12 13 14 15 16 17
18 19
20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61P B 0
P 3.2/E X I N T 0
P B 1
P 3.1/T X D
P B 2
P 3.0/R X D
P B 3
P B 4
P B 5
N C
V R E F
G N D
R E S E T -I N
P B 6
P B 7
R D ,C N T L 1
P 1.7/A D C 3
P S E N ,C N T L 2
W R ,C N T L 0
P 1.6/A D C 2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P A 7 P A 6 P 4.5/P W M 2 P A 5 P 4.4/P W M 1 P A 4 P 4.3/P W M 0 P A 3 G N D P 4.2/D C C V S Y N C P 4.1/D D C S C L P A 2 P 4.0/D D C S D A P A 1 P A 0 A D 0,P 0.0 A D 1,P 0.1 A D 2,P 0.2 A D 3,P 0.3 P 3.4/T 0AI05791
μPSD3200FAMILY PART NUMBERING
Table2.Ordering Information Scheme
For a list of available options(speed,package, etc.)or for further information on any aspect of this device,please contact your nearest ST Sales Of-fice.
Example:uPSD3234B V–24U6T
Device Type
uPSD=Microcontroller PSD
Family
3=8032core
PLD Size
2=16Macrocells
3=32Macrocells
SRAM Size
1=16Kbit
3=64Kbit
5=256Kbit
Main Flash Memory Size
3=1Mbit
4=2Mbit
5=4Mbit
IP Mix
A=USB,I2C,PWM,DDC,ADC,(2)UARTs
Supervisor(Reset Out,Reset In,LVD,WD)
B=I2C,PWM,DDC,ADC,(2)UARTs
Supervisor(Reset Out,Reset In,LVD,WD)
Operating Voltage
blank=V CC=4.5to5.5V
V=V CC=3.0to3.6V
Speed
24=24MHz
40=40MHz
Package
T=52-pin TQFP
U=80-pin TQFP
Temperature Range
1=0to70°C(commercial)
6=–40to85°C(industrial)
Option
T=Tape&Reel Packing
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μPSD3200FAMILY
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All other names are the property of their respective owners
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