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K7P163666A-HC33中文资料

Sep. 2003512Kx36 & 1Mx18 Synchronous Pipelined SRAM

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

Revision History

Rev. N o. Rev. 0.0 Rev. 0.1

Rev. 0.2

Rev. 0.3R emark

Advance Advance

Advance

Final

History

- Initial Document

- Absolute maximum ratings are changed V DD : 2.815 - > 3.13 V DDQ : 2.815 - > 2.4

V TERM : 2.815 - > VDDQ+0.5 (2.4V MAX)

- Recommended DC operating conditions are changed V REF / V CM -CLK : 0.68 - > 0.6, 0.95 - > 0.9- DC characteristics is changed I SBZZ : 150 - > 128

- AC Characteristics are changed

T AVKH / T DVKH / T WVKH / T SVKH : 0.4 / 0.5 / 0.5 - > 0.3 / 0.3 / 0.3 T KHAX / T KHDX / T KHWX / T KHSX : 0.5 / 0.5 / 0.5 - > 0.5 / 0.6 / 0.6

- Recommended DC operating condition is changed Max V DIF-CLK : V DDQ +0.3 -> V DDQ +0.6- Correct typo

V DD -> V DDQ : in MODE CONTROL at page4

D raft D ate Dec. 2001 Oct. 2002

Jan. 2003

Sep. 2003Document Title

Sep. 2003PIN DESCRIPTION

Pin Name Pin Description

K, K Differential Clocks

V REF HSTL Input Reference Voltage

SAn Synchronous Address Input M 1, M 2 Read Protocol Mode Pins ( M 1=V SS , M 2=V DDQ )DQn Bi-directional Data Bus

G Asynchronous Output Enable SW Synchronous Global Write Enable SS Synchronous Select SWa Synchronous Byte a Write Enable TCK JTAG Test Clock SWb Synchronous Byte b Write Enable TMS JTAG Test Mode Select SWc Synchronous Byte c Write Enable TDI JTAG Test Data Input SWd Synchronous Byte d Write Enable TDO JTAG Test Data Output

ZZ Asynchronous Power Down ZQ Output Driver Impedance Control V DD Core Power Supply V SS GND

V DDQ

Output Power Supply

No Connection

512Kx36 & 1Mx18 Synchronous Pipelined SRAM

FEATURES

Organization

Part Number Maximum Frequency Access Time 512Kx36

K7P163666A-HC33

333MHz 1.5 K7P163666A-HC30300MHz 1.6 K7P163666A-HC25250MHz 2.01Mx18

K7P161866A-HC33

333MHz 1.5 K7P161866A-HC30300MHz 1.6 K7P161866A-HC25

250MHz

2.0

FUNCTIONAL BLOCK DIAGRAM

SA[0:18] or SA[0:19]

SS SW

SWx

G 512Kx36

Data In ZZ DQx[1:9](x=a, b, c, d)or (x=a, b)

(x=a, b, c, d)or (x=a, b)

K CK

or 1Mx18Array R o w D e c o d e r

Column Decoder Write/Read Circuit

0 1

Data Out Register

Read Address Register

Write Address Register

Latch

SWx Register

? 512Kx36 or 1Mx18 Organizations.

? 2.5V Core/1.5V Output Power Supply (1.9V max V DDQ ).? HSTL Input and Output Levels.

? Differential, HSTL Clock Inputs K, K.? Synchronous Read and Write Operation ? Registered Input and Registered Output

? Internal Pipeline Latches to Support Late Write.

? Byte Write Capability(four byte write selects, one for each 9bits)? Synchronous or Asynchronous Output Enable.? Power Down Mode via ZZ Signal.

? Programmable Impedance Output Drivers.? JTAG 1149.1 Compatible Test Access port.

? 119(7x17)Pin Ball Grid Array Package(14mmx22mm).

PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7P163666A(512Kx36)

1234567

A V DDQ SA13SA10NC SA7SA4V DDQ

B N

C SA18SA9NC SA8SA17NC

C NC SA12SA11V D

D SA6SA5NC

D DQc8DQc9V SS ZQ V SS DQb9DQb8

E DQc6DQc7V SS SS V SS DQb7DQb6

F V DDQ DQc5V SS

G V SS DQb5V DDQ

G DQc3DQc4SWc NC SWb DQb4DQb3

H DQc1DQc2V SS NC V SS DQb2DQb1

J V DDQ V DD V REF V DD V REF V DD V DDQ

K DQd1DQd2V SS K V SS DQa2DQa1

L DQd3DQd4SWd K SWa DQa4DQa3 M V DDQ DQd5V SS SW V SS DQa5V DDQ

N DQd6DQd7V SS SA0V SS DQa7DQa6

P DQd8DQd9V SS SA1V SS DQa9DQa8

R NC SA15M1V DD M2SA2NC

T NC NC SA14SA16SA3NC ZZ

U V DDQ TMS TDI TCK TDO NC V DDQ

K7P161866A(1Mx18)

1234567

A V DDQ SA13SA10NC SA7SA4V DDQ

B N

C SA19SA9NC SA8SA17NC

C NC SA12SA11V D

D SA6SA5NC

D DQb1NC V SS ZQ V SS DQa9NC

E NC DQb2V SS SS V SS NC DQa8

F V DDQ NC V SS

G V SS DQa7V DDQ

G NC DQb3SWb NC NC NC DQa6

H DQb4NC V SS NC V SS DQa5NC

J V DDQ V DD V REF V DD V REF V DD V DDQ

K NC DQb5V SS K V SS NC DQa4

L DQb6NC NC K SWa DQa3NC

M V DDQ DQb7V SS SW V SS NC V DDQ

N DQb8NC V SS SA0V SS DQa2NC

P NC DQb9V SS SA1V SS NC DQa1

R NC SA15M1V DD M2SA2NC

T NC SA18SA14NC SA3SA16ZZ

U V DDQ TMS TDI TCK TDO NC V DDQ

Sep. 2003

FUNCTION DESCRIPTION

The K7P163666A and K7P161866A are 18,874,368 bit Synchronous Pipeline Mode SRAM. It is organized as 524,288 words of 36 bits(or 1,048,576 words of 18 bits)and is implemented in SAMSUNGs advanced CMOS technology.

Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

Read Operation

During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this cycle, signaling that the SRAM should drive out the data.

During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-ple SRAM cycles to perform a single read operation.

Write (Stire) Operation

All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock, one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.

Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is the same as the SW signal.

Bypass Read Operation

Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have new byte data from the write data buffer and the other bytes from the SRAM array.

Programmable Impedance Output Buffer Operation

This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM and V SS. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250?resistor will give an output buffer impedance of 50?. The allowable range of RQ is from 175? to 350?. Internal circuits evaluate and periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations. Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-tion by connecting ZQ to V SS or V DD.

Mode Control

There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined operating mode. For proper specified device operation, M1 must be connected to V SS and M2 must be connected to V DDQ. These mode pins must be set at power-up and must not change during device operation.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V SS, V DD, V DDQ, V REF, then V IN. V DD and V DDQ can be applied simultaneously, as long as V DDQ does not exceed V DD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: V IN, V REF, V DDQ, V DD, V SS. V DD and V DDQ can be removed simultaneously, as long as V DDQ does not exceed V DD by more than 0.5V during power-down.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated. Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

Sep. 2003

FUNCTION DESCRIPTION

The K7P163666A and K7P161866A are 18,874,368 bit Dual Mode (supports both Register Register and Late Select Mode) SRAM devices. They are organized as 524,288 words by 36 bits for K7P163666A and 1,048,576 words by 18 bits for K7P161866A, fabri-cated using Samsung's advanced CMOS technology. Late Write/Pipelined Read(RR) for x36/x18 organizations and Late Write/Late Select Read(LS) for x36 organization are supported.

The chip is operated with a single +2.5V power supply and is compatible wtih HSTL input and output. The package is 119(7x17) Plastic Ball Grid Array with balls on a 1.27mm pitch.

Read Operation for Register Register Mode(x36 and x18)

During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock. Read Operation for Late Select Mode(x36)

During read operations, addresses(SA) and controls except the Way Select Address(SAS) are registered during the first rising edge of K clock. The internal array(x72 bit data) is read between the first edge and the second edge, and as the Way Select Address(SAS) is registered at the second clock edge, x36 bit data is mux selected before the output register.

Write Operation(Late Write)

During write operations, addresses including the Way Select Address(SAS) and controls are registered at the first rising edge of K clock and data inputs are registered at the following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the timing of SW[a:d] is the same as the SW signal.

Bypass Read Operation

Programmable Impedance Output Buffer Operation

Mode Control

There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined operating mode. For proper specified device operation, M1 must be connected to V SS and M2 must be connected to V DD. These mode pins must be set at power-up and must not change during device operation.

Power-Up/Power-Down Supply Voltage Sequencing

Sleep Mode

Sep. 2003

TRUTH TABLE

K ZZ G SS SW SWa SWb SWc SWd DQa DQb DQc DQd Operation

X H X X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Power Down Mode. No Operation X L H X X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled.

↑L L H X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled.No Operation ↑L L L H X X X X D OUT D OUT D OUT D OUT Read Cycle

↑L X L L H H H H Hi-Z Hi-Z Hi-Z Hi-Z No Bytes Written

↑L X L L L H H H D IN Hi-Z Hi-Z Hi-Z Write first byte

↑L X L L H L H H Hi-Z D IN Hi-Z Hi-Z Write second byte

↑L X L L H H L H Hi-Z Hi-Z D IN Hi-Z Write third byte

↑L X L L H H H L Hi-Z Hi-Z Hi-Z D IN Write fourth byte

↑L X L L L L L L D IN D IN D IN D IN Write all bytes

NOTE : K & K are complementary

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Core Supply Voltage Relative to V SS V DD-0.5 to 3.13V

Output Supply Voltage Relative to V SS V DDQ-0.5 to 2.4V

Voltage on any I/O pin Relative to V SS V TERM-0.5 to V DDQ+0.5 (2.4V MAX)V

Output Short-Circuit Current I OUT25mA

Operating Temperature T OPR0 to 70°C

Storage Temperature T STG-55 to 125°C Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit Note Core Power Supply Voltage V DD 2.37 2.5 2.63V

Output Power Supply Voltage V DDQ 1.4 1.5 1.9V

Input High Level V IH V REF+0.1-V DDQ+0.3V

Input Low Level V IL-0.3-V REF-0.1V

Input Reference Voltage V REF0.60.750.9V

Clock Input Signal Voltage V IN-CLK-0.3-V DDQ+0.3V

Clock Input Differential Voltage V DIF-CLK0.1-V DDQ+0.6V

Clock Input Common Mode Voltage V CM-CLK0.60.750.9V

Sep. 2003

Sep. 2003DC CHARACTERISTICS

NOTE :1. Minimum cycle. I OUT =0mA.

2. 50% read cycles.

3. |I OH |=(V DDQ /2)/(RQ/5)±15% @V OH =V DDQ /2 for 175? ≤ RQ ≤ 350?.

4. |I OL |=(V DDQ /2)/(RQ/5)±15% @V OL =V DDQ /2 for 175? ≤ RQ ≤ 350?.

5. Programmable Impedance Output Buffer Mode. The ZQ pin is connected to V SS through RQ.

6. Minimum Impedance Output Buffer Mode. The ZQ pin is connected to V SS or V DD .

Parameter

Symbol Min Max Unit Note Average Power Supply Operating Current-x36(V IN =V IH or V IL , ZZ & SS=V IL )

I DD33I DD30I DD25-700620550mA

1, 2

Average Power Supply Operating Current-x18(V IN =V IH or V IL , ZZ & SS=V IL )I DD33I DD30I DD25-650570500mA 1, 2

Power Supply Standby Current (V IN =V IH or V IL , ZZ=V IH )

I SBZZ -128mA 1Active Standby Power Supply Current (V IN =V IH or V IL , SS=V IH , ZZ=V IL )I SBSS -200mA

Input Leakage Current (V IN =V SS or V DDQ )

I LI -11 μA Output Leakage Current

(V OUT =V SS or V DDQ , DQ in High-Z)

I LO -11 μA

Output High Voltage(Programmable Impedance Mode)V OH1V DDQ /2V DDQ V 3,5Output Low Voltage(Programmable Impedance Mode)V OL1V SS V DDQ /2V 4,5Output High Voltage(I OH =-0.1mA)V OH2V DDQ -0.2V DDQ V 6Output Low Voltage(I OL =0.1mA)V OL2V SS 0.2V 6Output High Voltage(I OH =-6mA)V OH3V DDQ -0.4V DDQ V 6Output Low Voltage(I OL =6mA)

V OL3

V SS

0.4

PIN CAPACITANCE

NOTE : Periodically sampled and not 100% tested.(T A =25°C, f=1MHz)

Parameter

Symbol Test Condition

Min Max Unit Input Capacitance C IN V IN =0V -4pF Data Output Capacitance

C OUT

V OUT =0V

-5

Sep. 2003AC TEST CONDITIONS (T A =0 to 70°C, V DD =2.37 -2.63V, V DDQ =1.5V)

NOTE : Parameters are tested with RQ=250? and V DDQ =1.5V.

Parameter

Symbol Value Unit Core Power Supply Voltage V DD 2.37~2.63

V Output Power Supply Voltage V DDQ 1.5V Input High/Low Level V IH /V IL 1.25/0.25V Input Reference Level V REF 0.75V Input Rise/Fall Time

T R /T F

0.5/0.5ns Input and Out Timing Reference Level 0.75V Clock Input Timing Reference Level

Cross Point

50?

AC TEST OUTPUT LOAD

25?

5pF

V DDQ /2

5pF

V DDQ /2

50?

V DDQ /2

AC CHARACTERISTICS

Parameter

Symbol -33-30

-25

Unit Note

Min Max Min Max Min Max Clock Cycle Time t KHKH 3.0- 3.3- 4.0-ns Clock High Pulse Width t KHKL 1.2- 1.3- 1.6-ns Clock Low Pulse Width t KLKH 1.2- 1.3- 1.6-ns Clock High to Output Valid t KHQV - 1.5- 1.6- 2.0ns Clock High to Output Hold t KHQX 0.5-0.5-0.5-ns Address Setup Time t AVKH 0.3-0.3-0.3-ns Address Hold Time t KHAX 0.5-0.6-0.6-ns Write Data Setup Time t DVKH 0.3-0.3-0.3-ns Write Data Hold Time t KHDX 0.5-0.6-0.6-ns SW, SW[a:d] Setup Time t WVKH 0.3-0.3-0.3-ns SW, SW[a:d] Hold Time t KHWX 0.5-0.6-0.6-ns SS Setup Time t SVKH 0.3-0.3-0.3-ns SS Hold Time

t KHSX 0.5-0.6-0.6-ns Clock High to Output Hi-Z t KHQZ - 1.5- 1.6- 2.0ns Clock High to Output Low-Z t KHQX10.5-0.5-0.5-ns G High to Output High-Z t GHQZ - 1.5- 1.6- 2.0ns G Low to Output Low-Z t GLQX 0.5-0.5-0.5-ns G Low to Output Valid

t GLQV - 1.5- 1.6- 2.0ns ZZ High to Power Down(Sleep Time)t ZZE -15-15-15ns ZZ Low to Recovery(Wake-up Time)

t ZZR

-20

SAn

SWx

DQn

SAn

SWx

DQn

Sep. 2003

SAn

SWx

DQn

Sep. 2003

Sep. 2003JTAG Instruction Coding

NOTE :

1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.

3. Bypass register is initiated to V SS when BYPASS instruction is invoked. The Bypass Register also holds serially loaded TDI when exiting the Shift DR states.

4. SAMPLE instruction does not places DQs in Hi-Z.

IR2IR1IR0Instruction TDO Output Notes 000 SAMPLE-Z Boundary Scan Register 1001 IDCODE Identification Register 2010 SAMPLE-Z Boundary Scan Register

1011 BYPASS Bypass Register 3100 SAMPLE Boundary Scan Register 4101 BYPASS Bypass Register 31

10 BYPASS Bypass Register 31

BYPASS

Bypass Register

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

TAP Controller State Diagram

JTAG Block Diagram

SRAM CORE

BYPASS Reg.Identification Reg.Instruction Reg.Control Signals

TAP Controller

TDO

M 2

M 1

TDI TMS TCK

Test Logic Reset

Run Test Idle

0010110

10111

000Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform-ance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Register, Bypass Register and ID register. The TAP control-ler has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required. It is possible to use this device without utilizing the TAP . To disable the TAP controller without interfacing with normal operation of the SRAM, TCK must be tied to V SS to preclude mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. But they may also be tied to V DD through a resistor. TDO should be left unconnected.

Sep. 2003ID REGISTER DEFINITION

Part Revision Number

(31:28)

Part Configuration

(27:18)

Vendor Definition

(17:12)

Samsung JEDEC Code

(11: 1)

Start Bit(0)

512Kx36000000111 00100XXXXXX 0000100111011Mx18

0000

01000 00011

XXXXXX

00001001110

BOUNDARY SCAN EXIT ORDER(x36)

363B SA 9SA 85B 35372B SA 18SA 176B 34383A SA 10SA 75A 33393C SA 11SA 65C 32402C SA 12SA 56C 31412A SA 13SA 46A 30422D DQc 9DQb 96D 29431D DQc 8DQb 87D 28442E DQc 7DQb 76E 27451E DQc 6DQb 67E 26462F DQc 5DQb 56F 25472G DQc 4DQb 46G 24481G DQc 3DQb 37G 23492H DQc 2DQb 26H 22501H DQc 1DQb 17H 21513G SWc SWb 5G 20524D ZQ G 4F 19534E SS K 4K 18544G NC*K 4L 17554H NC*SWa 5L 16564M SW DQa 17K 15573L SWd DQa 26K 14581K DQd 1DQa 37L 13592K DQd 2DQa 46L 12601L DQd 3DQa 56M 11612L DQd 4DQa 67N 10622M DQd 5DQa 76N 9631N DQd 6DQa 87P 8642N DQd 7DQa 96P 7651P DQd 8ZZ 7T 6662P DQd 9SA 35T 5673T SA 14SA 26R 4682R SA 15SA 164T 3694N SA 0SA 14P 270

M 1

M 2

BOUNDARY SCAN EXIT ORDER(x18)

263B SA 9SA 85B 25272B SA 19SA 176B 24283A SA 10SA 75A 23293C SA 11SA 65C 22302C SA 12SA 56C 2131

SA 13

SA 46A 20DQa 9

321D DQb 133

DQb 2

DQa 87E 18DQa 7

DQb 3

DQa 67G 16DQa 5

351H DQb 4363G SWb 374D ZQ G 4F 14384E SS K 4K 13394G NC K 4L 12404H NC SWa 5L 1141

DQa 4

422K DQb 5DQa 3

DQb 6

442M DQb 7DQa 26N 845

DQb 8

DQa 1

ZZ 7T 6462P DQb 9SA 35T 5473T SA 14SA 2

482R SA 15494N SA 0SA 14P 3502T SA 18SA 166T 251

M 1

M 2

SCAN REGISTER DEFINITION

Part Instruction Register

Bypass Register

ID Register Boundary Scan

512Kx36 3 bits 1 bits 32 bits 70 bits 1Mx18

3 bits

1 bits

32 bits

51 bits

NOTE :1. Pins 4G and 4H are no connection pin to internal chip. The scanned data are fixed to "0" and "1" respectively.

Sep. 2003

Sep. 2003119 BGA PACKAGE DIMENSIONS

0.750±0.15

1.27

12.50±0.10

0.60±0.10

1.50REF C1.00

C0.70

14.00±0.10

22.00±0.10

20.50±0.10

NOTE :

1. All Dimensions are in Millimeters.

2. Solder Ball to PCB Offset : 0.10 MAX.

3. PCB to Cavity Offset : 0.10 MAX.

Indicator of

Ball(1A) Location

119 BGA PACKAGE THERMAL CHARACTERISTICS

NOTE : 1. Junction temperature can be calculated by : T J = T A + P D x Theta_JA.

Parameter

Symbol Thermal Resistance

Unit Note Junction to Ambient(at still air)Theta_JA TBD °C/W 1W Heating

Junction to Case Theta_JC TBD °C/W Junction to Board

Theta_JB

TBD

°C/W

2W Heating